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AM3357: Difference in placement of .cinit between compiler version V18.12.x and V20.2.x...

André Wetzel
Prodigy 140 points
Part Number: AM3357

Hi,

we have a special entry (.image_endtoken ) at the end of the firmware image which is placed by the following linker command file. In the compiler version V18.12.x  and lower.cinit is placed before .image_endtoken, but in compiler version V20.2.x it is placed after!

How can we stop this behavior?

Thanks,

André

MEMORY
{
  // SRAM (Total 63kB)
  SRAM_CACHELOCK_MEM : ORIGIN = 0x402F0400 LENGTH = 0x00008000
  // SRAM (31kB)
  SRAM_MEM : ORIGIN = 0x402F8400 LENGTH = 0x00007C00

  // L3 OCMC0 (64kB)
  OCMC0_MEM : ORIGIN = 0x40300000 LENGTH = 0x00010000
  // External DDR3 SDRAM (Total 256MB)
  DDR_CACHELOCK_MEM : ORIGIN = 0x80000000 LENGTH = 0x00010000 // (64kB: 0xc18d8c)
  // DDR3 SDRAM
  DDR_MEM : ORIGIN = 0x80010000 LENGTH = 0x0FFF0000
}

SECTIONS
{
  .init : {  AM335x_CodeStart.obj (.text) } LOAD > 0x80000000

  .cinit : LOAD > DDR_MEM

  GROUP : LOAD > DDR_MEM
  {
    .text // Code

    .data

    .const
    .image_endtoken
  }

}

  • 0
    TI__Guru*** 125366 points

    Hi Andre,

    What software do you use on AM3357? which version?

    What is the compiler? I don't recognize the version number v18.12 or v20.2.

  • 0 in reply to Bin Liu
    Prodigy 140 points

    It's CCS V10.4.0 with the Compiler version TI v20.2.5.LTS and v18.12.5.LTS...

  • 0 in reply to André Wetzel
    Prodigy 140 points

    Map file with TI v20.2.5.LTS

    SEGMENT ALLOCATION MAP

    run origin load origin length init length attrs members
    ---------- ----------- ---------- ----------- ----- -------
    402f0400 80080e34 0000000c 0000000c r-x
    402f0400 80080e34 0000000c 0000000c r-x .text_SRAM
    402f8400 80080dfc 00000038 00000038 r-x
    402f8400 80080dfc 00000038 00000038 r-x .text_vect
    80000000 80000000 000000d0 000000d0 r-x
    80000000 80000000 000000d0 000000d0 r-x .init
    80000100 80000100 0000d5c4 0000d5c4 rwx
    80000100 80000100 0000d5c4 0000d5c4 rwx .text_ddr_realtime
    80010000 80010000 0004556c 0004556c r-x
    80010000 80010000 0004556c 0004556c r-x .text
    80055570 80055570 000041be 00000000 rw-
    80055570 80055570 000041be 00000000 rw- .data
    80059730 80059730 000276cc 000276cc r--
    80059730 80059730 000276c6 000276c6 r-- .const
    80080df8 80080df8 00000004 00000004 r-- .image_endtoken
    80080e40 80080e40 00001368 00001368 r--
    80080e40 80080e40 00001368 00001368 r-- .cinit
    8e388000 8e388000 00002800 00000000 rw-
    8e388000 8e388000 00002000 00000000 rw- .sysmem
    8e38a000 8e38a000 00000800 00000000 rw- .stack
    8e38c000 8e38c000 01c7318c 00000000 rw-
    8e38c000 8e38c000 01c7318c 00000000 rw- .bss

    Map file with TI v18.12.5.LTS

    SEGMENT ALLOCATION MAP

    run origin load origin length init length attrs members
    ---------- ----------- ---------- ----------- ----- -------
    402f0400 80010000 0000000c 0000000c r-x
    402f0400 80010000 0000000c 0000000c r-x .text_SRAM
    402f8400 8001000c 00000038 00000038 r-x
    402f8400 8001000c 00000038 00000038 r-x .text_vect
    80000000 80000000 000000d0 000000d0 r-x
    80000000 80000000 000000d0 000000d0 r-x .init
    80000100 80000100 0000d7bc 0000d7bc rwx
    80000100 80000100 0000d7bc 0000d7bc rwx .text_ddr_realtime
    80010048 80010048 00001354 00001354 r--
    80010048 80010048 00001354 00001354 r-- .cinit
    80018000 80018000 00045554 00045554 r-x
    80018000 80018000 00045554 00045554 r-x .text
    8005d558 8005d558 000041be 00000000 rw-
    8005d558 8005d558 000041be 00000000 rw- .data
    80061718 80061718 000276cc 000276cc r--
    80061718 80061718 000276c6 000276c6 r-- .const
    80088de0 80088de0 00000004 00000004 r-- .image_endtoken
    8e388000 8e388000 00002800 00000000 rw-
    8e388000 8e388000 00002000 00000000 rw- .sysmem
    8e38a000 8e38a000 00000800 00000000 rw- .stack
    8e38c000 8e38c000 01c7318c 00000000 rw-
    8e38c000 8e38c000 01c7318c 00000000 rw- .bss

  • 0 in reply to André Wetzel
    TI__Guru*** 125366 points

    Hi Andre,

    I am routing your question to our RTOS expert, but he is out of office this week, please expect delayed response.

  • 0
    TI__Guru**** 232790 points

    I do not have a test case which allows me to test whether my suggestion resolves the problem.  But I am confident enough to ask you to please try it.

    Add the linker option --cinit_compression=off and put .cinit inside the GROUP.  The .cinit section is used to initialize .data, which is in the GROUP.  Furthermore, by default, the .cinit section is compressed.  This compression requires that the contents, location, and size of the .data section be known.  If .cinit and .data are in the same GROUP, this creates a loop of circular processing.  It can only be broken by not compressing .cinit.  For further detail, please see this forum thread.

    Please let me know if this suggestion resolves the problem.

    Thanks and regards,

    -George

  • 0 in reply to George Mock
    Prodigy 140 points

    Thanks al lot, George!
    This solved my issue and worked for both compiler versions.

    Regards,
    André