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AM4379: McSPI 0 single channel Read with Force not working

Part Number: AM4379
Other Parts Discussed in Thread: SYSBIOS

AM4379 McSPI not working in; 4 wire, Single Channel, Master Mode during read operation. All write operations work correctly.  I am communicating to a Microchip KSZ9477 7-port Ethernet switch over SPI.  The Sitara is in master mode and the switch is a slave. I have verified with a Scope that the Sitara transmits the correct data and that the KSZ device responds correctly.  However, the Sitara always reads zero at the Rx register.  I have tried an interrupt driven driver, a polled driver, both using and not using FIFO buffers.  Nothing works.  I have also tried various Tx/Rx clock rates and all four POL/PHA combinations.  In all cases write work perfectly but reads always return zero.

MCSPI_CH0CONF Register = 0x2006_0CFC (also tried setting Bits[13:12] separately with write followed by read).  Bit[20] is FORCE bit and this is set at start of operation and cleared at end of operation.  All combinations of POL and PHA tried.

 

Register configuration after first (of 5) words sent and RX Full.  RX always read zero?

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

  • This is a stand-alone (bare-metal) test program and is NOT using SysBios, NDK, PDK, or any other Ti package.  This is a custom board. The memory interface was developed using the Ti Memory Configuration Tool and has been thoroughly tested and works properly.  I have verified that the PINMUX register setting for the SPI device – and all other devices are correct using the debugger and register display tool.  The test program was developed under Code Composer Studio Version: 10.2.0.00009

  • This is a stand-alone (bare-metal) test program and is NOT using SysBios, NDK, PDK, or any other Ti package.  This is a custom board. The memory interface was developed using the Ti Memory Configuration Tool and has been thoroughly tested and works properly.  I have verified that the PINMUX register setting for the SPI device – and all other devices are correct using the debugger and register display tool.  The test program was developed under Code Composer Studio Version: 10.2.0.00009

  • PROBLEM SOLVED: (by luck).

    I changed the default PINMUX configuration for the SPI_SCLK signal to enable input CONF_SPI0_D1_RXACTI

    VE = 1 and the reads now work.  The Ti PINMUX tools setup the SCLK signal incorrectly and enabling the SCLK read bit does not seem to be mentioned in the TRM anywhere that I could find.:

           /* SPI3 -> spi0_sclk -> P23 */

           PIN_SPI0_SCLK, 0, \

           ( \

               PIN_MODE(0) | \

               ((PIN_PULL_UD_DIS | PIN_PULL_UP_EN | PIN_RX_ACTIVE | PIN_DS_VALUE_OVERRIDE_EN | PIN_DS_OP_DIS | PIN_DS_PULL_UP_EN) & \

               (~PIN_DS_OP_VAL_1 & ~PIN_DS_PULL_UD_EN & ~PIN_WAKE_UP_EN))

           ) \

        },

    Final Register Values: 

    CTRL_CONF_SPI0_SCLK 0x13070000         Memory Mapped                (originally 0x1303_0000)

    CTRL_CONF_SPI0_D0     0x13030000         Memory Mapped           

    CTRL_CONF_SPI0_D1     0x13070000         Memory Mapped           

    CTRL_CONF_SPI0_CS0   0x13030000         Memory Mapped