TMDS243GPEVM: TMDS243GPEVM issues

Links

Part Number: TMDS243GPEVM

Hi Team

My situation is summarized as follows:
Development board: tmds243gpevm
CCS version: v10.4.00006
Emulator: xds560v2
SDK version: MCU_ plus_ sdk_ am243x_ 08_ 00_ 00_ twenty-one
The problems encountered are as follows:
1. After 12V power supply, switch SW1 is turned to on, and the development board has no output of 5V and 3.3V. After using external 5V power supply to supply power to 5V test point and ground, the board has normal 5V and 3.3V output
2. At present, all programs cannot be downloaded, including the routines provided by Ti SDK. The download error information is as follows
MAIN_ Cortex_ R5_ 0_ 0: Trouble Writing Memory Block at 0x0 on Page 0 of Length 0x40: (Error -1065 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration,
power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MAIN_ Cortex_ R5_ 0_ 0: File Loader: Verification failed: Target failed to write 0x00000000
MAIN_ Cortex_ R5_ 0_ 0: GEL: File: F:\Am243x\J7_ V2\prj\app\Debug\app.out: Load failed.
A few days ago, I could download the program normally. During debugging, I pressed the reset button (SW4), the debugging was interrupted, and then the program could not be downloaded. During this period, there was no change in the program code and engineering configuration.
3. When DDR is used (after initializing DDR with gel file), the peripheral clock enable success signal cannot be obtained. Because it cannot be simulated now, the call stack cannot be provided. The specific implementation sequence is
SystemInit() ->PowerClock_ init() ->Module_ clockEnable() ->SOC_ moduleClockEnable() ->Sciclient_ pmGetModuleState() ->Sciclient_ service() ->Sciclient_ waitForMessage()
When entering sciclient_ After the waitformessage() function, the program falls into a loop waiting.
However, as long as DDR is not initialized with gel file, the same program runs normally.
I have two development boards in my hand. The situation of the two development boards is the same.
The main problems encountered now are the above three. Problems 1 and 3 can be avoided temporarily. The more urgent problem is problem 2. Please see what the problem will be and whether there are any solutions. Thank you.

over 2 years ago

0 Links over 2 years ago

TI__Intellectual 2145 points

If I comment out line 15 of the. CMD file
-e_ vectors /* This is the entry of the application, _ vector MUST be plabed starting address 0x0 */
The program can be downloaded, but it doesn't work properly.
I think it may be because after commenting out the above, the default interrupt handler will be used.
However, I need to use RTOS, so RTOS needs to take over the interrupt service processing and change the interrupt vector handler.

7181.linker.cmd.txt

/* This is the stack that is used by code running within main()
 * In case of NORTOS,
 * - This means all the code outside of ISR uses this stack
 * In case of FreeRTOS
 * - This means all the code until vTaskStartScheduler() is called in main()
 *   uses this stack.
 * - After vTaskStartScheduler() each task created in FreeRTOS has its own stack
 */
--stack_size=16384
/* This is the heap size for malloc() API in NORTOS and FreeRTOS
 * This is also the heap used by pvPortMalloc in FreeRTOS
 */
--heap_size=32768
-e_vectors  /* This is the entry of the application, _vector MUST be plabed starting address 0x0 */

/* This is the size of stack when R5 is in IRQ mode
 * In NORTOS,
 * - Here interrupt nesting is disabled as of now
 * - This is the stack used by ISRs registered as type IRQ
 * In FreeRTOS,
 * - Here interrupt nesting is enabled
 * - This is stack that is used initally when a IRQ is received
 * - But then the mode is switched to SVC mode and SVC stack is used for all user ISR callbacks
 * - Hence in FreeRTOS, IRQ stack size is less and SVC stack size is more
 */
__IRQ_STACK_SIZE = 256;
/* This is the size of stack when R5 is in IRQ mode
 * - In both NORTOS and FreeRTOS nesting is disabled for FIQ
 */
__FIQ_STACK_SIZE = 256;
__SVC_STACK_SIZE = 4096; /* This is the size of stack when R5 is in SVC mode */
__ABORT_STACK_SIZE = 256;  /* This is the size of stack when R5 is in ABORT mode */
__UNDEFINED_STACK_SIZE = 256;  /* This is the size of stack when R5 is in UNDEF mode */

SECTIONS
{
    /* This has the R5F entry point and vector table, this MUST be at 0x0 */
    .vectors:{} palign(8) > R5F_VECS

    /* This has the R5F boot code until MPU is enabled,  this MUST be at a address < 0x80000000
     * i.e this cannot be placed in DDR
     */
    GROUP {
        .text.hwi: palign(8)
        .text.cache: palign(8)
        .text.mpu: palign(8)
        .text.boot: palign(8)
        .text:abort: palign(8) /* this helps in loading symbols when using XIP mode */
    } > MSRAM

    /* This is rest of code. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .text:   {} palign(8)   /* This is where code resides */
        .rodata: {} palign(8)   /* This is where const's go */
    } > MSRAM

    /* This is rest of initialized data. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .data:   {} palign(8)   /* This is where initialized globals and static go */
    } > MSRAM

    /* This is rest of uninitialized data. This can be placed in DDR if DDR is available and needed */
    GROUP {
        .bss:    {} palign(8)   /* This is where uninitialized globals go */
        RUN_START(__BSS_START)
        RUN_END(__BSS_END)
        .sysmem: {} palign(8)   /* This is where the malloc heap goes */
        .stack:  {} palign(8)   /* This is where the main() stack goes */
    } > MSRAM

    /* This is where the stacks for different R5F modes go */
    GROUP {
        .irqstack: {. = . + __IRQ_STACK_SIZE;} align(8)
        RUN_START(__IRQ_STACK_START)
        RUN_END(__IRQ_STACK_END)
        .fiqstack: {. = . + __FIQ_STACK_SIZE;} align(8)
        RUN_START(__FIQ_STACK_START)
        RUN_END(__FIQ_STACK_END)
        .svcstack: {. = . + __SVC_STACK_SIZE;} align(8)
        RUN_START(__SVC_STACK_START)
        RUN_END(__SVC_STACK_END)
        .abortstack: {. = . + __ABORT_STACK_SIZE;} align(8)
        RUN_START(__ABORT_STACK_START)
        RUN_END(__ABORT_STACK_END)
        .undefinedstack: {. = . + __UNDEFINED_STACK_SIZE;} align(8)
        RUN_START(__UNDEFINED_STACK_START)
        RUN_END(__UNDEFINED_STACK_END)
    } > MSRAM

    /* General purpose user shared memory, used in some examples */
    .bss.user_shared_mem (NOLOAD) : {} > USER_SHM_MEM
    /* this is used when Debug log's to shared memory are enabled, else this is not used */
    .bss.log_shared_mem  (NOLOAD) : {} > LOG_SHM_MEM
    /* this is used only when IPC RPMessage is enabled, else this is not used */
    .bss.ipc_vring_mem   (NOLOAD) : {} > RTOS_NORTOS_IPC_SHM_MEM
    /* General purpose non cacheable memory, used in some examples */
    .bss.nocache (NOLOAD) : {} > NON_CACHE_MEM
}

/*
NOTE: Below memory is reserved for DMSC usage
 - During Boot till security handoff is complete
   0x701E0000 - 0x701FFFFF (128KB)
 - After "Security Handoff" is complete (i.e at run time)
   0x701FC000 - 0x701FFFFF (16KB)

 Security handoff is complete when this message is sent to the DMSC,
   TISCI_MSG_SEC_HANDOVER

 This should be sent once all cores are loaded and all application
 specific firewall calls are setup.
*/

MEMORY
{
    R5F_VECS  : ORIGIN = 0x00000000 , LENGTH = 0x00000040
    R5F_TCMA  : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
    R5F_TCMB0 : ORIGIN = 0x41010000 , LENGTH = 0x00008000

    /* memory segment used to hold CPU specific non-cached data, MAKE to add a MPU entry to mark this as non-cached */
    NON_CACHE_MEM : ORIGIN = 0x70060000 , LENGTH = 0x8000

    /* when using multi-core application's i.e more than one R5F/M4F active, make sure
     * this memory does not overlap with other R5F's
     */
    MSRAM     : ORIGIN = 0x70080000 , LENGTH = 0x40000

    /* This section can be used to put XIP section of the application in flash, make sure this does not overlap with
     * other CPUs. Also make sure to add a MPU entry for this section and mark it as cached and code executable
     */
    FLASH     : ORIGIN = 0x60100000 , LENGTH = 0x80000

    DDR       : ORIGIN = 0x80000000 , LENGTH = 0x1000000

    /* shared memory segments */
    /* On R5F,
     * - make sure there is a MPU entry which maps below regions as non-cache
     */
    USER_SHM_MEM            : ORIGIN = 0x701D0000, LENGTH = 0x00004000
    LOG_SHM_MEM             : ORIGIN = 0x701D4000, LENGTH = 0x00004000
    RTOS_NORTOS_IPC_SHM_MEM : ORIGIN = 0x701D8000, LENGTH = 0x00008000
}

0 Prasad Jondhale over 2 years ago in reply to Links

TI__Mastermind 27743 points

Hi,

I suspect board (or some parts especially DDR) is damaged because of connecting the wrong power supply. Are you able to see all the LED's blinking on the EVM?

As you mentioned your DDR is not initializing correctly which is an issue if you app is using DDR. We need to resolve DDR initialization issue first.

Can you share output of gel files? are you using CCS boot or OSPI boot mode?

Regards,

Prasad

0 woody w over 2 years ago in reply to Prasad Jondhale

Prodigy 100 points

hi, my GEL output is like this

i first connect core m3, and then connect core r5_0_0

DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals...
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done.
DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done.
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN
DMSC_Cortex_M3_0: GEL Output: No change needed.
DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F.
DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F
DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done.
DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done.
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output:
MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output:

DDR not initialized with R5 connect.

Go to menu Scripts --> AM24 DDR Initialization -> AM24_DDR_Initialization_ECC_Disabled to initialize DDR.

====

MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is in progress ... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> ECC Disabled <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
MAIN_Cortex_R5_0_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
MAIN_Cortex_R5_0_0: GEL Output: Setting DDR4 frequency...
MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from PI...
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI initialization started... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from CTL...
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR CTL initialization started... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Polling PI DONE bit...
MAIN_Cortex_R5_0_0: GEL Output: pi_int_status = 0x29C02001...
MAIN_Cortex_R5_0_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - Not documented bit set.
MAIN_Cortex_R5_0_0: GEL Output: ctl_int_status = 0x02000000...
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR Initialization completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR4 Initialization is DONE! <<<---
MAIN_Cortex_R5_0_0: Trouble Writing Memory Block at 0x0 on Page 0 of Length 0x40: (Error -1065 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MAIN_Cortex_R5_0_0: File Loader: Verification failed: Target failed to write 0x00000000
MAIN_Cortex_R5_0_0: GEL: File: F:\Am243x\eth\workspace\enet_lwip_cpsw_am243x-evm_r5fss0-0_freertos_ti-arm-clang\Debug\enet_lwip_cpsw_am243x-evm_r5fss0-0_freertos_ti-arm-clang.out: Load failed.

0 Prasad Jondhale over 2 years ago in reply to woody w

TI__Mastermind 27743 points

Are you doing this manually or using script provided in SDK?

Please note that you need to load & run the system firmware image and board config application before loading your application.

Now, if you are using SBL NULL in the flash, you don't need to connect and run gels except DDR configuration.

AM243x MCU+ SDK: CCS Launch, Load and Run (ti.com)

Regards,

Prasad

0 woody w over 2 years ago in reply to Prasad Jondhale

Prodigy 100 points

thanks for you reply.

But I must init DDR with GEL script when the project need DDR, such as sdk project "enet_lwip_cpsw_am243x-evm_r5fss0-0_freertos_ti-arm-clang"

and it worked correct 1 week ago, but failed now

The most important problem is i can't download any program now(with or without ddr), output like this

MAIN_Cortex_R5_0_0: Trouble Writing Memory Block at 0x0 on Page 0 of Length 0x40: (Error -1065 @ 0x0) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.4.0.00129)
MAIN_Cortex_R5_0_0: File Loader: Verification failed: Target failed to write 0x00000000

0 Prasad Jondhale over 2 years ago in reply to woody w

TI__Mastermind 27743 points

Are you using SBL NULL with boot from flash?

If yes, you don't need to load any other gel but only DDR config one.

I see you are doing all soc initialization again.

0 woody w over 2 years ago in reply to Prasad Jondhale

Prodigy 100 points

my boot pin config is uart now

0 Prasad Jondhale over 2 years ago in reply to woody w

TI__Mastermind 27743 points

Please follow the steps as mentioned in the MCU+ SDK getting started guide. You need to use "SOC Initialization Using CCS Scripting".

AM243x MCU+ SDK: EVM Setup (ti.com)

0 woody w over 2 years ago in reply to Prasad Jondhale

Prodigy 100 points

Sending sbl_prebuilt/am243x-evm/sbl_uart_uniflash.release.tiimage: 329280bytes [
Sending sbl_prebuilt/am243x-evm/sbl_uart_uniflash.release.tiimage: 329280bytes [
Sending sbl_prebuilt/am243x-evm/sbl_uart_uniflash.release.tiimage: 330309bytes [
Sending sbl_prebuilt/am243x-evm/sbl_uart_uniflash.release.tiimage: 330310bytes [

Sent flashwriter sbl_prebuilt/am243x-evm/sbl_uart_uniflash.release.tiimage of si
ze 328444 bytes in 31.56s.

Executing command 2 of 2 ...
Command arguments : --file=sbl_prebuilt/am243x-evm/sbl_null.release.tiimage --op
eration=flash --flash-offset=0x0
Sending sbl_prebuilt/am243x-evm/sbl_null.release.tiimage: 0%| | 2/232988 [01:
[ERROR] XMODEM send failed, no response OR incorrect response from EVM OR cancel
led by user,
Power cycle EVM and run this script again !!!

successed with step 1, failed in step 2,i tried many times

and i have done this before, and 2 step successed

0 woody w over 2 years ago in reply to Prasad Jondhale

Prodigy 100 points

I have another question, i can;t find mmcsd driver in the sdk,where can i get the mmcsd driver?

thanks

0 Prasad Jondhale over 2 years ago in reply to woody w

TI__Mastermind 27743 points

mmcsd driver would be released in 8.1 release (scheduled end of this month).

Processors

Processors forum

TMDS243GPEVM: TMDS243GPEVM issues