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DRA829V: LPDDR4 Simulation

Junpei Kishi
Intellectual 865 points
Part Number: DRA829V
Other Parts Discussed in Thread: DRA829

Hi team,

I would like to ask some questions regarding to LPDDR4 simulation showed by "spracn9b.pdf".
https://www.ti.com/lit/an/spracn9b/spracn9b.pdf

Question 1

In page.19 of "spracn9b.pdf," we can see that we have to know the on-die decoupling capacitance on the DDR supply net for both controller and DRAM.
However, sometimes we can't get the DRAM's package model including power source pads.
In this case, can we evaluate the simulation connecting power source only to SoC?

Question 2

Regarding Fig 3-11 in page.27, we can see Vix_CK_Ratio is mentioned by "Vix_CA Ratio".
Could you explain Vix_CA mean?

Question 3

Regarding Fig 3-11 in page.27, we can see we have to evaluate ring-back margins at high/low levels.
However, I couldn't find ring-back limitation or specification in JESD209-4.
https://www.jedec.org/sites/default/files/docs/JESD209-4.pdf
Could you explain which limitation matched to this evaluation item?

Question 4

Regarding to evaluation items, do we have to consider PVT conditions when configuring EYE pattern mask to test DQ, CA, CS Signals?
If we have to consider output variation from SoC due to PVT conditions, please let me know which document can be reference.

Question 5

Regarding evaluation items in page 27,  we can see there is a peak to peak power noise evaluation.
Is this means that we have to confirm Vpp of DDR power lines fits absolute maximum ratings shown in DRA829 datasheets?

Thanks and Best Regards,
Junpei Kishi

  • +1
    TI__Mastermind 39320 points

    Question 1:  Not including the power component of the DRAM model will impact simulation accuracy, as the power supply noise (at DRAM) will not be accounted for in the simulation.

    Question 2:  See section 3.5.3.2 Eye Quality for description of Vix_DQS.  Vix_CK is similar, just for the CK waveform rather than DQS.

    Question 3:  This is not  a JEDEC spec. A positive ring-back margin adds confidence that there are no glitches that can cause a bit error. 

    Question 4: PVT for the SoC is account for in the various IBIS model settings.

    Question 5: Yes, the power supply noise (Vpp) must meet ratings defined in datasheets

  • 0 in reply to Robert Eschler
    TI__Intellectual 865 points

    Hi Robert,

    Thanks for your replying, and please let me ask additional questions regarding Q3.
    Is there any reference for ring-back margins?
    How much is the margin which we can decide it's positive?

    Regards,
    Junpei

  • +1 in reply to Junpei Kishi
    TI__Mastermind 39320 points

    Recommend using our sample simulations for estimates on ring-back margins.  There is no 'minimum' margin required.

  • 0 in reply to Robert Eschler
    TI__Intellectual 865 points

    Hi Robert,

    Could you let me ask additional questions?

    Q1

    In p.28 of spracn9b.pdf, we can see "Data read simulations need to be verified at SOC."
    In my understanding, "at SOC" means we have to verify at IBIS model edge.
    But is it right? Or, it means at Pkg model edge?

    Q2

    Some eye diagrams can be seen on spracn9b.pdf as Fig.3-5 ~ Fig.3-7, but these eye diagrams have been considered the effect of cross talking?
    If the design met a S-parameter specification which is showed in p.17, can we discard cross talking when we evaluate the simulated eye diagram?

    Q3

    I understand that IBIS model includes PVT variation, but not output timing variation of DQ/DQS.
    Should I consider for these timing variations?

     

    Thanks and Best Regards,
    Junpei Kishi

  • 0 in reply to Junpei Kishi
    TI__Mastermind 39320 points

    Q1 - Data read simulations are verified at the SoC Die (not the SoC pad).

    Q2 - Cross talk is include in the simulations we show, and should be included in customer simulations.

    Q3 - data timing is not part of these simulations