Hi experts,
I'd like to know about MPU_IRQ_xx.
The link below describes how to set the UART3 interrupt to DSP2.
e2e.ti.com/.../am5726-setup-a-rtos_template_app_am572x_c66-project-for-dsp2
/*
* AM5 DSP does not have a default Xbar connection for UART
* interrupt, need the following Xbar interrupt configuration
*/
/* Use reserved DSP1_IRQ_34 */
CSL_xbarDspIrqConfigure(2,
CSL_XBAR_INST_DSP2_IRQ_34,
CSL_XBAR_UART3_IRQ);
And TRM describes MPU_IRQ_xx as follows.
That is, DSP can select DSP1 or DSP2, but not MPU. Are peripheral interrupts always sent to two Arm cores (a15-0 and a15-1)?
Best regards,
Sasaki
