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AM5726: Regarding MPU_IRQ_xx

Part Number: AM5726

Hi experts,

I'd like to know about MPU_IRQ_xx.

The link below describes how to set the UART3 interrupt to DSP2.

* AM5 DSP does not have a default Xbar connection for UART
* interrupt, need the following Xbar interrupt configuration
/* Use reserved DSP1_IRQ_34 */


And TRM describes MPU_IRQ_xx as follows.

That is, DSP can select DSP1 or DSP2, but not MPU. Are peripheral interrupts always sent to two Arm cores (a15-0 and a15-1)?

Best regards,