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66AK2H14: PCIe and MPAX issue

Part Number: 66AK2H14

Hello

My custom board based on evmK2H is configured as follow

C66x core0 acting as PCI ROOT Complex, FPGA is endpoint

During PCI init, DSP open BAR1 (size 256 MB) starting at address 0x6000_0000 (this is DDR3B) and setup inbound translation region.
FPGA has internal DMA that write/read to/from BAR1. After each operation completed (read or write) , FPGA send IRQ to DSP
This configuration (CONFIG_1) works as expected, FPGA write data to DDR3B and send IRQ to DSP ... read operation works the same.

LEt's change a little bit configuration (CONFIG_2), DSP open BAR1 at address 0x8000_0000: this is DDR3A because MPAX registers (segment 1)
contains 0x800000BF and 0x8000001E
This configuration still works as expected ... FPGA read/Write data and send IRQ


Third configuration (CONFIG_3):  I changed MPAX register to map DDR3B at 0x8000_0000. New MPAX resgisters values: 0x080000BF and 0x8000001E
(remap is ok , writing a number at 0x6000_0000 --> found the same number at 0x8000_0000); BAR1 at 0x8000_0000 (now this is DDR3B)

Unfortunately, using this configuration, FPGA cant access BAR1. DSP doesn't receive IRQ from FPGA, meaning that dma fails to write or read data.

short recap:

CONFIG_1:   BAR1 at 0x6000_0000  (DD3B)  -->OK

CONFIG_2:   BAR1 at 0x8000_0000  (DD3A)  -->OK

CONFIG_3:   BAR1 at 0x8000_0000  (DD3B)  -->NOT OK

Any idea on what is wrong with CONFIG_3???

Regards,

Fabio