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TMDS64GPEVM: M4F Access problem launch script CCS

Part Number: TMDS64GPEVM
Other Parts Discussed in Thread: SYSCONFIG

Hello Ming,

I've noticed connection problems to M4F by executing launch script in CCS. Does the SOC always have to be initialized via SBL_OSPI_NULL bootloader to connect to the M4F core with CCS? Is it not possible to run the launch script in no-boot mode and then connect to the M4F (as with the R5 cores)? Can you give us a little more insight into why this is not possible?

Best Regards,

Benjamin

  • Hi Benjamin,

    Using launch.js along with the CCS on no-boot mode should work, but we do recommend using the SBL NULL for OSPI or from the SD card. It is more reliable and closer to the real application scenario. What is the reason for you to insist on the CCS wih launch.js? 

    Best regards,

    Ming

  • Hi Ming,

    booting sbl null from ospi flash is working. We can connect to all r5f cores and also to m4f. But starting debugging in NoBoot Mode and using the launch script within CCS, we cannot connect to m4f core - the XDS110 debugger is hanging, and we have to restart CCS and do a powercycle the XDS110. 

    We don't insist on using the launch script, but we would like to know if it works or not! On the other hand, it can also be convenient to boot in noboot mode and initialize the SOC via launch script...

    Best regards,

      Benjamin  

  • Hi Benjamin,

    Again what is the reason you will need to use the no-boot mode and the launch.js?

    Which MCU+ SDK are you using, when you see this problem?

    Best regards,

    Ming

  • we are using mcu plus sdk 8.01.00

  • 8.01.00.25 - the latest one?

    I will try it it with the 8.01.00.25 and get back to you.

    I still do not understand why you have to use the CCS with launch.js.

  • Hi Benjamin,

    I tried the CCS with launch.js on AM64x EVM with no-boot mode. It connects to both R5F0_0 and M4 without any issue. Here are the steps:

    1. Set the AM64x EVM to no-boot mode: SW2: on on off on on on on on and SW3: off off off off off off off off off.

    2. Launch the target configuration file for AM64x EVM

    3. Open the script console 

    4.. LoadJSFile(C:\ti\mcu_plus_sdk_am64x_08_01_00_25\tools\ccs_load\am64x_am243x\load_dmsc.js")

    5. "Connect Target" Cortex_M4F_0

    Best regards,

    Ming

  • Hi Ming,
     
    I also used this new launch script. I start my SoC into NoBoot Mode and start this launch script. when it has finished , I directly connect to the M4F. At this moment nothing works anymore. CCS is not responding. I'm just able to close the window. But also here CCS is not responding. I have to force shutdown of CCS. Then I reboot SoC and want to connect with CCS, but here I don't get any connection from XDS110. I don't know which process is running in background, but the debugger is not accessible anymore until I make a reboot of my computer. And working from remote, this could lead to not be able to connect to the computer again. Maybe there is some USB problem with the XDS110. Also running xdsdfu reset does not work.
     
    But Benjamin and I managed to connect to M4F from NoBoot and with running the new launch script. But in this case we connected first to R5 Cores, M3 Core then to M4F core.
     
    So connection order was following: NoBoot->LauchScript->Connect R5_0_0->Connect R5_0_1->Connect R5_1_0->Connect R5_1_1->Connect M3->Connect M4
     
     
    Kind regards
     
    Andreas

  • Hi Andreas,

    It sounds like your launch.js did not complete for some reason.

    Can you show  the output of your script console and CCS console?

    I also have the same question: why don't you use the SBL NULL for OSPI or SD card?

    Best regards,

    Ming

  • why don't you use the SBL NULL for OSPI or SD card?

    Why are you providing a launch script? Also SD Card is no option. We don't have a sd card on our PCB.

    Usually it is very comfortable and practical to use a launch script. We don't need to flash any bootloader. For development it would be very easy to only use the launch script. After implementing some functions, start connecting to SoC, run launch script and start debugging.

    Flashing SBL requires the SoC to be configured for the particular flash device. At the moment we have 3 flash devices. So some developers have different flash devices.

    So it would be very nice if the launch script would work properly for ALL Cores!

  • Hi Ming,

    our workflow is as follows:

    1. Bootpins are set to: primary boot OSPI, bup boot mode UART

    2. no sbl is written into flash

    3. Powerup board (ROM falls into bup bootmode UART, we can see it over the UART0 terminal. "C" are comming)

    4. no we can connect to r5_0_0 over CCS and set the boot mode manually to no boot by setting register CTRLMMR_MAIN_DEVSTAT (0x4300 0030h) to 0x0000 007B.

    5. Then we do a WARMRESET by setting reset control register CTRLMMR_RST_CTRL(0x4301 8170) to  0x000200F6 --> the Registers have to be unlocked

    5. After that WARMRESET we are executing the launch script

    6. Now we are ready for connecting the cores.

    After that procedure we are able to connect to all R5 cores and can execute an application. Connecting to M4_0 the debugger crashes. If we connect to the M3_0 first and then to the M4_0, the connection works and the debugger does not crash. But running an application on the M4_0 does not work either - System_init() is not returning, see call stack attached.

    Kind regards,

    Benjamin

  • output of our script console:

    js:> loadJSFile ("/home/scheufeleb/src/BNI-Develop/Debug/Script/launch_am64x_bni_basic.js")
    Connecting to DMSC_Cortex_M3_0!
    Fill R5F ATCM memory...
    Writing While(1) for R5F
    Loading DMSC Firmware ... /home/scheufeleb/src/BNI-Develop/modules/ti-sitara-support-package/TI_sdk/mcu_plus_sdk_am64x/source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
    DMSC Firmware Load Done...
    DMSC Firmware run starting now...
    Connecting to MCU Cortex_R5_0!
     Main Boot Mode is 120
    Running the board configuration initialization from R5!
    Happy Debugging!!

  • Hey Ming,

    I`ve made some test with the launch script and recognized, that it can deal with the OSPI primary boot mode. So my previous post is obsolete ;-) the scripting output looks like:

    js:> loadJSFile ("/home/scheufeleb/src/BNI-Develop/Debug/Script/launch_am64x_bni_basic.js")
    Connecting to DMSC_Cortex_M3_0!
    Fill R5F ATCM memory...
    Writing While(1) for R5F
    Loading DMSC Firmware ... /home/scheufeleb/src/BNI-Develop/modules/ti-sitara-support-package/TI_sdk/mcu_plus_sdk_am64x/source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
    DMSC Firmware Load Done...
    DMSC Firmware run starting now...
    Connecting to MCU Cortex_R5_0!
    Main Boot Mode is 8
    Disable MCU Timer for ROM clean up
    Running Async
    Running the board configuration initialization from R5!
    Happy Debugging!!

    That`s not resolving the connection problem to the M4 core. You have to connect to the M3 first before you go to the M4, otherwise the debugger crashes. Executing a simple application with UART log enable, System_init() is not returning. Disable UART log in sysconfig, then the application is running and we see the log messages on the CCS console.

    Regards,

    Benjamin

  • Hi Benjamin,

    I noticed that you were using the OSPI primary boot mode while you using the launch.js. You were also use your own launch.js (launch_am64x_bni_basic.js). Can you use the no-boot mode and TI provided launch_dmsc.js instead.

    Here is the script console output:

    js:> LoadJSFile(C:\ti\mcu_plus_sdk_am64x_08_01_00_25\tools\ccs_load\am64x_am243x\load_dmsc.js")
    Connecting to DMSC_Cortex_M3_0!
    Fill R5F ATCM memory...
    Writing While(1) for R5F
    Loading DMSC Firmware ... C:/ti/mcu_plus_sdk_am64x_08_01_00_25/source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
    DMSC Firmware Load Done...
    DMSC Firmware run starting now...
    Connecting to MCU Cortex_R5_0!
    Main Boot Mode is 120
    Running the board configuration initialization from R5!
    Happy Debugging!!

    Here is the CCS console output:

    DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
    DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
    DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
    DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to [0x6000_0000, 0x4000_0000].
    DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
    DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
    DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
    DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
    DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
    DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
    DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
    DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
    DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
    DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals...
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done.
    DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done.
    DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals.
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done.
    DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done.
    DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
    DMSC_Cortex_M3_0: GEL Output:
    DMSC_Cortex_M3_0: GEL Output: *****DDR is configured using R5 or A53 GELs
    DMSC_Cortex_M3_0: GEL Output: M4F WFI Vector set into IRAM.
    MAIN_Cortex_R5_0_0: GEL Output: CPU reset (soft reset) has been issued through GEL.

    Here is another CCS console CIO output:

    [MAIN_Cortex_R5_0_0]
    DMSC Firmware Version 21.5.0--v2021.05 (Terrific Llam
    DMSC Firmware revision 0x15
    DMSC ABI revision 3.1

    [SCICLIENT] ABI check PASSED
    [SCICLIENT] Board Configuration with Debug enabled ...
    [SCICLIENT] Common Board Configuration PASSED
    [SCICLIENT] PM Board Configuration PASSED
    [SCICLIENT] RM Board Configuration PASSED
    [SCICLIENT] Security Board Configuration PASSED

    DMSC Firmware Version 21.5.0--v2021.05 (Terrific Llam
    DMSC Firmware revision 0x15
    DMSC ABI revision 3.1

    All tests have passed!!.

    As you can see the M4F was powered on properly:

    DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F

    Best regards,

    Ming

  • Hi Kishan,

    I also build and load the M4F example empty (m4fss0-0_freertos). It works fine. Please make sure the UART output is not print out on MAIN UART0, but MCU UART0. And by default, you should get the CCS console output too. Make sure all 4 UART from J26 are connected to the terminal emulator.

    Best regards,

    Ming

  • Sorry it's not resolved!

  • Hey Ming,

    I can recreate this on the eval board, I have the problem on our own board!

    On the evm everything works fine! On our custom board we have these problems. The output of the launch-srcipt looks the same, except for the boot mode. We use OSPI as primary boot mode. The launch sript should know how to handle it - I have tested it on the evm board with success!

    DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F

    What exactly do the two lines mentioned do? Perhaps we still have a problem with the reset circuit of the MCU-Reset...

    Here are the console outputs from our board:

    js:> loadJSFile ("/home/scheufeleb/src/BNI-Develop/Debug/Script/launch_am64x_bni_basic.js")
    Connecting to DMSC_Cortex_M3_0!
    Fill R5F ATCM memory...
    Writing While(1) for R5F
    Loading DMSC Firmware ... /home/scheufeleb/src/BNI-Develop/modules/ti-sitara-support-package/TI_sdk/mcu_plus_sdk_am64x/source/drivers/sciclient/soc/am64x_am243x/sysfw.bin
    DMSC Firmware Load Done...
    DMSC Firmware run starting now...
    Connecting to MCU Cortex_R5_0!
     Main Boot Mode is 8
    Disable MCU Timer for ROM clean up
    Running Async
    Running the board configuration initialization from R5!
    Happy Debugging!!


    DMSC_Cortex_M3_0: GEL Output: This GEL is currently only supported for use from the Cortex-M3 inside the DMSC.
    DMSC_Cortex_M3_0: GEL Output: Do not run this GEL from any other CPU on the SoC.
    DMSC_Cortex_M3_0: GEL Output: This script sets the first address translation region to [0x8000_0000, 0x0000_0000].
    DMSC_Cortex_M3_0: GEL Output: It also sets the second address translation region to    [0x6000_0000, 0x4000_0000].
    DMSC_Cortex_M3_0: GEL Output: This is consistent with the SoC DV assumptions.
    DMSC_Cortex_M3_0: GEL Output: Configuring ATCM for the R5Fs
    DMSC_Cortex_M3_0: GEL Output: ATCM Configured.
    DMSC_Cortex_M3_0: GEL Output: R5F Halt bits set.
    DMSC_Cortex_M3_0: GEL Output: Configuring bootvectors
    DMSC_Cortex_M3_0: GEL Output: Bootvectors configured.
    DMSC_Cortex_M3_0: GEL Output: Programming all PLLs.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 0 (Main PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 0 (Main PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 12 (DDR PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 12 (DDR PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming Main PLL 14 (Main Domain Pulsar) PLL)
    DMSC_Cortex_M3_0: GEL Output: Main PLL 14 (Main Domain Pulsar PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: Programming MCU PLL 0 (MCU PLL)
    DMSC_Cortex_M3_0: GEL Output: MCU PLL 0 (MCU PLL) Set.
    DMSC_Cortex_M3_0: GEL Output: All PLLs programmed.
    DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains in progress...
    DMSC_Cortex_M3_0: GEL Output: Powering up MAIN domain peripherals...
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DMSC
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_TEST
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN_PBIST
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_4B
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMMC_8B
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_USB
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ADC
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_DEBUGSS
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_GPMC
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_CFG
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_EMIF_DATA
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCAN_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SA2UL
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_SERDES_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PCIE_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_CLUSTER_0_PBIST
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_CLUSTER_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_A53_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_A53_1 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_0
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_0_R5_1
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_1_R5_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_PULSAR_PBIST_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_PULSAR_1 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_0
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_0 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_ICSSG_1
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_ICSSG_1 done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_CPSW3G
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_CPSW done.
    DMSC_Cortex_M3_0: GEL Output: Powering up all MAIN domain peripherals done.
    DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals.
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_TEST
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MAIN2MCU
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_MCU2MAIN
    DMSC_Cortex_M3_0: GEL Output: No change needed.
    DMSC_Cortex_M3_0: GEL Output: Powering up GP_CORE_CTL_MCU done.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F.
    DMSC_Cortex_M3_0: GEL Output: Powering up LPSC_M4F
    DMSC_Cortex_M3_0: GEL Output: Power domain and module state changed successfully.
    DMSC_Cortex_M3_0: GEL Output: Powering up PD_M4F done.
    DMSC_Cortex_M3_0: GEL Output: Powering up MCU Domain peripherals done.
    DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
    DMSC_Cortex_M3_0: GEL Output:
    DMSC_Cortex_M3_0: GEL Output: *****DDR is configured using R5 or A53 GELs
    DMSC_Cortex_M3_0: GEL Output: M4F WFI Vector set into IRAM.
    MAIN_Cortex_R5_0_0: GEL Output: Running from R5
    MAIN_Cortex_R5_0_0: GEL Output:

    DDR not initialized with R5 connect.

    Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.

    ====

    [MAIN_Cortex_R5_0_0]
    DMSC Firmware Version 21.5.0--v2021.05 (Terrific Llam
    DMSC Firmware revision 0x15
    DMSC ABI revision 3.1

    [SCICLIENT] ABI check PASSED
    [SCICLIENT] Board Configuration with Debug enabled ...
    [SCICLIENT] Common Board Configuration PASSED
    [SCICLIENT] PM Board Configuration PASSED
    [SCICLIENT] RM Board Configuration PASSED
    [SCICLIENT] Security Board Configuration PASSED

    DMSC Firmware Version 21.5.0--v2021.05 (Terrific Llam
    DMSC Firmware revision 0x15
    DMSC ABI revision 3.1

    All tests have passed!!

  • Hi Benjamin,

    Have tried the empty (m4fss0-0_freertos) on your board?

    The other difference I saw in your launch.js is that in AM64x EVM target configuration R5F0_0 is using the CPU_reset.gel, but your target configuration is using the AM64x_GP_EVM.gel for R5F0_0, because it called the DDR_init() instead.

    ----------------------------
    MAIN_Cortex_R5_0_0: GEL Output: CPU reset (soft reset) has been issued through GEL.
    ----------------------------
    vs
    ----------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Running from R5
    MAIN_Cortex_R5_0_0: GEL Output:

    DDR not initialized with R5 connect.

    Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.
    -----------------------------
    Best regards,
    Ming

  • Hi Ming,

    Have tried the empty (m4fss0-0_freertos) on your board?

    we are working with the empty m4fss0-0_nortos example... and with the sbl_ospi_null bootloader we can connect to m4f and load/run the example successfully. With the launch script provided by the SDK 08.01.00 we have the connection problems discussed for the connection to the m4f core on our own custom board.

    I can't explain the difference in the GEL output. We use the launch script from the SDK (tools/ccs_load/am64x_am243x/load_dmsc.js).  Do we still have to adapt our target configarution file  so that no DDR is initialized?

    another observation:
    If we stop the debug session after execution the load_dmsc.js script (sysfirmware should be loaded to m3) and then relaunch the target configuration we can connect to m4 without any issues and run the example application. In this case the debug probe is not chrashing!

    Kind regards,

    Benjamin

  • Hi Benjamin,

    Both R5F_0_0 and M4F_0 are using ..\..\emulation\gel\AM64x\CPU_reset.gel:

    Best regards,

    Ming