Due to the U.S. Thanksgiving holiday, please expect delayed responses during the week of 11/22.

AM5728: Linux on A15 - RTOS on IPU1-0 (M4) - Map RTOS app in right memory region

Part Number: AM5728

Hi,
I'm trying to start a simple RTOS application (blink led) on IPU1-0 (Cortex-M4) from linux running on A15 thanks to the fact to copy my app here /lib/firmware/dra7-ipu1-fw.xem4
I've an issue with the fact that my RTOS app is not mapped at the correct address as define in .dtsi file

ipu1_memory_region: ipu1-memory@95800000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0x95800000 0x0 0x2000000>;
		reusable;
		status = "okay";
};

I'm able to load the M4 RTOS application with CSS without linux and run it on M4 but the execution address is in range 0x80000000.
How can I setup my .cfg file in CSS to map .text part into correct area to be able to run it correctly with linux ?

  • Hi,

    I try to use the ipu1-0 ex01_hello available in the ipc module of the RTOS SDK. and problem is that I'm not able to use it in CCS.
    I've mount and use the rtos_template_app_am572x_m4 present in the pdk module and all work fine. I'm able to load and debug the application but this application can not be started from linux. why ?

    I read a lot of documentation like (sprac60.pdf, Running_RTOS_on_Cortex_M4_SLIDES.pdf, etc...) and post in e2e forum, but it's appears that I'm not able to run my application on Cortex M4 started from linux (A15) 

    I would like to know, if I can found a clear basic explanation (documentation, training) of which module we have to use, how configure it and why ?

    Thanks in advance

    Regards,

    Quentin

  • Hi Quentin,

    Apologies for delay here.

    I'm able to load the M4 RTOS application with CSS without linux and run it on M4 but the execution address is in range 0x80000000.
    How can I setup my .cfg file in CSS to map .text part into correct area to be able to run it correctly with linux ?

    To map the execution address range in .cfg file of CCS to linux DTS node, you need to create a bld file for changing the execution address of the application.

    The bld file for ARM is already available in the <PDKInstallPath>\packages\ti\build\am572x. Create a bld file for M4 same as ARM and change the APP_CODE_ADDR value to map with the Linux DTS file. In your case it should be 0x95800000. 

    Modify the GPIO_LedBlink_idkAM571x_m4TestProject.txt to include the newly created M4 bld file which will override the default configurations. Please refer to <PDKInstallPath>\packages\ti\drv\usb\example\bios\am57xxUSB_DevBulk_idkAM571x_armExampleProject.txt from USB_DevBulk example project.

    Regards, 

    Parth

  • Hi Parth,

    No problem for the delay, I've delay also. Thanks for your response.

    So, I've again some issues, dues to the fact that in fact I not sure to understand how the matching between the .cfg, .bld and the generate linker script is done.
    What I did:

    I added in my project config_am572x.bld file and setup the xdc tools to use it, like this (config.bld and setup)

    SBL_SIZE                = 4*KB;
    DDR3_ADDR_0             = 0x80000000 + SBL_SIZE;
    DDR3_ADDR_1             = 0xA0000000;
    
    APP_CODE_SIZE                   = 2*MB - SBL_SIZE;
    APP_CACHED_DATA_SIZE            = 20*MB;
    APP_CACHED_DATA_BLK1_SIZE       = 244*MB;
    APP_CACHED_DATA_BLK2_SIZE       = 128*MB;
    APP_UNCACHED_DATA_BLK3_SIZE     = 2*MB;
    
    APP_CODE_ADDR                   = DDR3_ADDR_0;
    APP_CACHED_DATA_ADDR            = APP_CODE_ADDR + APP_CODE_SIZE;
    APP_CACHED_DATA_BLK1_ADDR       = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
    APP_CACHED_DATA_BLK2_ADDR       = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
    APP_UNCACHED_DATA_BLK3_ADDR     = DDR3_ADDR_1;
    
    Build.platformTable[myplatform] =
    {
        externalMemoryMap:
        [
            ["APP_CODE_MEM", {
                comment : "APP_CODE_MEM",
                name    : "APP_CODE_MEM",
                base    : APP_CODE_ADDR,
                len     : APP_CODE_SIZE
            }],
            ["APP_CACHED_DATA_MEM", {
                comment : "APP_CACHED_DATA_MEM",
                name    : "APP_CACHED_DATA_MEM",
                base    : APP_CACHED_DATA_ADDR,
                len     : APP_CACHED_DATA_SIZE
            }],
            ["APP_UNCACHED_DATA_BLK3_MEM", {
                comment : "APP_UNCACHED_DATA_BLK3_MEM",
                name    : "APP_UNCACHED_DATA_BLK3_MEM",
                base    : APP_UNCACHED_DATA_BLK3_ADDR,
                len     : APP_UNCACHED_DATA_BLK3_SIZE
            }],
            ["APP_CACHED_DATA_BLK1_MEM", {
                comment : "APP_CACHED_DATA_BLK1_MEM",
                name    : "APP_CACHED_DATA_BLK1_MEM",
                base    : APP_CACHED_DATA_BLK1_ADDR,
                len     : APP_CACHED_DATA_BLK1_SIZE
            }],
            ["APP_CACHED_DATA_BLK2_MEM", {
                comment : "APP_CACHED_DATA_BLK2_MEM",
                name    : "APP_CACHED_DATA_BLK2_MEM",
                base    : APP_CACHED_DATA_BLK2_ADDR,
                len     : APP_CACHED_DATA_BLK2_SIZE
            }],
        ],
        codeMemory: "APP_CODE_MEM",
        dataMemory: "APP_CACHED_DATA_MEM",
        stackMemory: "APP_CACHED_DATA_MEM"
    };

    Then to test in my main.cfg file I configure to place ".text" into "APP_CODE_MEM"

    /* ================ Memory sections configuration ================ */
    Program.sectMap["BOARD_IO_DELAY_DATA"] = "OCMC_RAM1";
    Program.sectMap["BOARD_IO_DELAY_CODE"] = "OCMC_RAM1";
    Program.sectMap[".text"] = "APP_CODE_MEM";

    So when I build the project, I've an error that tell me

    "configPkg/linker.cmd", line 166: warning #10097: memory range not found: APP_CODE_MEM on page 0
    "configPkg/linker.cmd", line 166: error #10265: no valid memory range(null) available for placement of ".text"
    "configPkg/linker.cmd", line 166: error #10099-D: program will not fit into available memory.  placement with alignment fails for section ".text" size 0xce13 

    Then I look the generated linker.cmd and its appears that the memory section are not defined like I ask with my .bld file

    /* C6x Elf symbols */
    --symbol_map __TI_STACK_SIZE=__STACK_SIZE
    --symbol_map __TI_STACK_BASE=__stack
    --symbol_map _stack=__stack
    
    
    
    --args 0x0
    -heap  0x0
    -stack 0x1000
    
    MEMORY
    {
        L2_ROM : org = 0x0, len = 0x4000
        L2_RAM : org = 0x20000000, len = 0x10000
        OCMC_RAM1 : org = 0x40300000, len = 0x80000
        OCMC_RAM2 : org = 0x40400000, len = 0x100000
        OCMC_RAM3 : org = 0x40500000, len = 0x100000
        EXT_RAM : org = 0x80000000, len = 0x80000000
    }
    
    ......
    ......
    
    /*
     * symbolic aliases for static instance objects
     */
    xdc_runtime_Startup__EXECFXN__C = 1;
    xdc_runtime_Startup__RESETFXN__C = 1;
    
    SECTIONS
    {
        .text: load >> APP_CODE_MEM
        .stack: load > EXT_RAM
        GROUP: load > EXT_RAM
        {
            .bss:
            .neardata:
            .rodata:
        }
        .binit: load > EXT_RAM
        .cinit: load > EXT_RAM
        .init_array: load > EXT_RAM
        .const: load >> EXT_RAM
        .data: load >> EXT_RAM
        .fardata: load >> EXT_RAM
        .switch: load >> EXT_RAM
        .sysmem: load > EXT_RAM
        .far: load >> EXT_RAM
        .args: load > EXT_RAM align = 0x4, fill = 0 {_argsize = 0x0; }
        .cio: load >> EXT_RAM
        .ARM.exidx: load > EXT_RAM
        .ARM.extab: load >> EXT_RAM
        BOARD_IO_DELAY_DATA: load > OCMC_RAM1
        BOARD_IO_DELAY_CODE: load > OCMC_RAM1
        .bootVecs:  type = DSECT
        .resetVecs: load > 0x400
        .vecs: load > 0x400, type = DSECT
        .ducatiBoot: load > 0x0
        .ducatiGates: load > 0x7f0, type = NOINIT
        xdc.meta: load > EXT_RAM, type = COPY
    
    }

    It's seem that the section placement is take in account by not the memory definition.
    There is something that I don't understand with the generate linker, how can I change memory definition on it ?
    Do I have to write my own linker script ? but this is not the goal when we use xdc tools , right ?

    Thanks in advance

    Regards,

    Quentin