RE: AM6442: How to check and set the PRU core frequency in Linux?

xixiguohx

Other Parts Discussed in Thread: TEST

Hi Nick,

During the Linux OS startup, the ICSSG1 PRU0 frequency will be initialized according to dts configuration, right? I want to change the ICSSG1 PRU0 frequency in dts, where should I modify?

I found these configuration in kernel dts files,

icssg1_coreclk_mux: coreclk-mux@3c {
reg = <0x3c>;
#clock-cells = <0>;
clocks = <&k3_clks 82 0>, /* icssg1_core_clk */
<&k3_clks 82 20>; /* icssg1_iclk */
assigned-clocks = <&icssg1_coreclk_mux>;
assigned-clock-parents = <&k3_clks 82 20>;
};

82 means device id:

82	AM6_DEV_CBASS0

0 means clock id:

0	DEV_BOARD0_BUS_SCL3_IN

Are these right?

If yes, how does it be used to config the ICSSG1 PRU0 frequency?

Best Regards

xixiguo

6 months ago

0 Nick Saulnier 6 months ago

TI__Mastermind 38830 points

Hello,

I will have time to look at this tomorrow. Please ping the thread if I have not replied by Monday.

Regards,

Nick

0 xixiguohx 6 months ago in reply to Nick Saulnier

Intellectual 400 points

Hi Nick,

Is there any updates for this topic?

I can config as below to choose to use icssg1_core_clk,

But the PLL2_HSDIV_CTRL0 register(0x682080) value is 0x8007, that means the ICSSG1 PRU0 frequency is 225Mhz.

Where to change the PLL2_HSDIV_CTRL0 configure in dts files? I want to change it to 0x8005.

Best Regards

xixiguo

0 Ethan Tian 6 months ago in reply to Nick Saulnier

TI__Prodigy 310 points

Hi Nick

I would like to ask if there are any updates here

BR.

Ethan

0 Nick Saulnier 5 months ago in reply to Ethan Tian

TI__Mastermind 38830 points

Apologies for the delayed response here folks. Every time I think I have a minute to dig into this I run out of time. Responding to get this back to the top of my queue for when I log back in tomorrow.

-Nick

0 xixiguohx 4 months ago in reply to Nick Saulnier

Intellectual 400 points

Hi Nick,

Merry Christmas!

Is there any updates?

Best Regards

xixiguo

0 Nick Saulnier 4 months ago in reply to xixiguohx

TI__Mastermind 38830 points

Hello Xixiguo,

Happy new year! Thank you for your patience here. It is pretty late at night here, so I am going to toss up some resources and ideas while I am looking at your thread and we can talk about details later.

References:
arch/arm64/boot/dts/ti/k3-am64-main.dtsi <-- this is where we define the clock muxing with coreclk-mux
Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml <-- coreclk-mux node defined here

https://downloads.ti.com/tisci/esd/latest/5_soc_doc/am64x/clocks.html section Clocks for PRU_ICSSG0 Device defines the clock numbers

Device: AM64X_DEV_PRU_ICSSG0 (ID = 81)
Device: AM64X_DEV_PRU_ICSSG1 (ID = 82)

However, it does not look like we explicitly documented how to set the PRU core clock from the devicetree anywhere. This is what I think would work based on an example from a different processor:

                                icssg0_coreclk_mux: coreclk-mux@3c {
                                        reg = <0x3c>;
                                        #clock-cells = <0>;
                                        clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
                                                 <&k3_clks 81 20>; /* icssg0_iclk */
                                        assigned-clocks = <&k3_clks 81 0>, <&icssg0_coreclk_mux>;
                                        assigned-clock-parents = <&k3_clks 81 X>, <&k3_clks 81 0>;
                                };
                
                Where X is 1 or 2 depending on whether you want to select
                MAIN_2_HSDIVOUT0_CLK
                MAIN_0_HSDIVOUT9_CLK

But I have not tested it at this point, and you would also need to control the clock frequency settings for MAIN_2_HSDIVOUT0_CLK or MAIN_0_HSDIVOUT9_CLK if you were using them (or use ICLK for 250MHz frequency, see https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1041347/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-ccs for more)

I still need to check with the developers on whether this is the "right" way to do it, or if there is a better way to control PRU core clocks from Linux.

Regards,

Nick

0 xixiguohx 4 months ago in reply to Nick Saulnier

Intellectual 400 points

Hi Nick,

Thanks for your reply!

Yes, I also need to control the clock frequency settings for MAIN_2_HSDIVOUT0_CLK. So please continue to help on this topic, thank you!

I'm wondering that maybe if it should be initialized the MAIN_2_HSDIVOUT0_CLK in uboot. I found in SDK8.0 uboot source code arch/arm/mach-k3/j7200 or arch/arm/mach-k3/j721e, they both have clk-data.c to specific clock platform data. But Am64x does not have such similar clk configure. Maybe you can also help to check this?

Best Regards

xixiguo

0 Nick Saulnier 4 months ago in reply to xixiguohx

TI__Mastermind 38830 points

Hello Xixiguo,

Ok, I made some more progress decoding Documentation/devicetree/bindings/clock/clock-bindings.txt.

I think this is how things work, but I do not have time to test before I leave for a short vacation. If you are able to give it a try before I am, please provide feedback on whether anything could be improved. Then we can use what we figure out to finally fill in https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1049800/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-linux

Explanation

A clock mux is represented in the devicetree file with a node. For AM64x the clock mux nodes are named icssgX_coreclk_mux and icssgX_iepclk_mux, but for this explanation we'll use the terms in this diagram:

input1 -->|
...    -->|
inputY -->| clk_mux --> output --> PRU core
...    -->|
inputN -->|

For this clock mux, our clock mux node would look like this:

clk_mux_node {
    clocks = <input1>,
             ...
             <inputN>;
	assigned-clocks = <&clk_mux_node>; // this is "output"
	assigned-clock-parents = <inputY>; the clock parent of "output" is selected from input1:inputN
	assigned-clock-rates = <frequency_in_Hz_of_output>; // not needed for fixed frequency sources like VCLK
}

That seems simple enough, right? Select one of the inputs to clk_mux (inputY), and set the input as the clock-parent of the output. If needed, set the frequency in assigned-clock-rates.

However, the PRU clock source is not always that simple. Let's say we are using the AM64x, we want to run code that we copied from AM335x, and we want the code to run EXACTLY the same. Then we need the PRU core clock to run at 200MHz. For that, we need to set MAIN_PLL0_HSDIV9_CLKOUT = 200MHz, then mux MAIN_PLL0_HSDIV9_CLKOUT --> ICSSGn_CORE_CLK --> CORE_CLOCK.

Now we have two levels of muxing that we need to do. Our diagram looks like this:

in1 -->|                 input1 -->|
... -->|                 ...    -->|
inY -->|-> clk_mux_2 --> inputY -->|-> clk_mux --> output --> PRU core
... -->|                 ...    -->|
inN -->|                 inputN -->|

Instead of creating a separate node for clk_mux2, you just add that mux information into the clk_mux node.

clk_mux_node {
    clocks = <input1>,
             ...
             <inputN>;
	assigned-clocks = <inputY>, <&clk_mux_node>;
	assigned-clock-parents = <inY>, <inputY>; // inY parents inputY, inputY parents &clk_mux_node
	assigned-clock-rates = <frequency_in_Hz_of_output>, <0>; // set inputY to the expected frequency
}

Notice that we need to use assigned-clock-rates if the clock source can be set to multiple frequencies. So if we need MAIN_PLL0_HSDIV9_CLKOUT = 200MHz, then we need to set
assigned-clock-rates = <200000000>, <0>;
Linux now knows to set output 9 of MAIN_PLL0 to 200MHz.

Example

Let's continue with the example from the explanation:
* AM64x, where the PRU cores in ICSSG0 need to run at 200MHz
* Set MAIN_PLL0_HSDIV9_CLKOUT = 200MHz
* Mux MAIN_PLL0_HSDIV9_CLKOUT --> ICSSG0_CORE_CLK --> CORE_CLOCK

                                icssg0_coreclk_mux: coreclk-mux@3c {
                                        reg = <0x3c>;
                                        #clock-cells = <0>;
                                        clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
                                                 <&k3_clks 81 20>; /* icssg0_iclk */
                                        assigned-clocks = <&k3_clks 81 0>, <&icssg0_coreclk_mux>;
                                        assigned-clock-parents = <&k3_clks 81 2>, <&k3_clks 81 0>; /* DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK */
                                        assigned-clock-rates = <200000000>, <0>; /* 200MHz */
                                };

NOTE! At this point, I have not looked into whether there are tools to see if another part of the processor is using that clock source. It is up to you to make sure that if you are specifically setting a clock frequency, that 1) no other part of the processor uses that clock source, or 2) that you designed your system so that all users of that clock source expect the new frequency.

Other useful tools

How do I see what the current clock settings are from Linux?

First off, you need to know the Device IDs and Clock IDs used by TISCI. If we check here:
https://downloads.ti.com/tisci/esd/latest/5_soc_doc/am64x/clocks.html
Then we see that AM64x ICSSG0 is Device ID 81, and ICSSG1 is Device ID 82.

Go to the AM64x EVM terminal. You can check the kernel clk_summary:

#

clock --------------------------------------- . . . clk:82:20 30080000.icssg.coreclk-mux 30080000.icssg.iepclk-mux       0 clk:82:11 clk:82:10 clk:82:9 clk:82:8 clk:82:7 clk:82:6 clk:82:5 clk:82:4 clk:82:3 clk:82:2 clk:82:1 clk:82:0 clk:81:20 30000000.icssg.coreclk-mux 30000000.icssg.iepclk-mux       0 clk:81:11 clk:81:10 clk:81:9 clk:81:8 clk:81:7 clk:81:6 clk:81:5 clk:81:4 clk:81:3 clk:81:2 clk:81:1 clk:81:0

cat /sys/kernel/debug/clk/clk_summary enable  prepare  protect                                duty count    count    count        rate   accuracy phase  cycle ------------------------------------------------------ 0        0        0   250000000          0     0  50000 0        0        0   250000000          0     0  50000 0        0   250000000          0     0  50000 0        0        0   500000000          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0   200000000          0     0  50000 0        0        0   225000000          0     0  50000 0        0        0   225000000          0     0  50000 0        0        0   333333333          0     0  50000 0        0        0   225000000          0     0  50000 0        0        0   225000000          0     0  50000 0        0        0   250000000          0     0  50000 0        0        0   250000000          0     0  50000 0        0   250000000          0     0  50000 0        0        0   500000000          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0           0          0     0  50000 0        0        0   200000000          0     0  50000 0        0        0   225000000          0     0  50000 0        0        0   225000000          0     0  50000 0        0        0   333333333          0     0  50000 0        0        0   225000000          0     0  50000 0        0        0   225000000          0     0  50000

This tells us that both PRU Core clock and IEP timer clock are using the VCLK clock source (Clock ID 20) for ICSSG0 and ICSSG1. We expect VCLK to run at 250MHz, and the "rate" confirms this clock frequency. This clock muxing matches the default k3-am64-main.dtsi devicetree settings:

                                icssg0_coreclk_mux: coreclk-mux@3c {
                                        reg = <0x3c>;
                                        #clock-cells = <0>;
                                        clocks = <&k3_clks 81 0>,  /* icssg0_core_clk */
                                                 <&k3_clks 81 20>; /* icssg0_iclk */
                                        assigned-clocks = <&icssg0_coreclk_mux>;
                                        assigned-clock-parents = <&k3_clks 81 20>;
                                };

                                icssg0_iepclk_mux: iepclk-mux@30 {
                                        reg = <0x30>;
                                        #clock-cells = <0>;
                                        clocks = <&k3_clks 81 3>,       /* icssg0_iep_clk */
                                                 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */
                                        assigned-clocks = <&icssg0_iepclk_mux>;
                                        assigned-clock-parents = <&icssg0_coreclk_mux>;
                                };

You can also use k3conf to dump a list of clocks and their frequencies:

# k3conf dump clocks

|---------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                                                           | Status              | Clock Frequency |
|---------------------------------------------------------------------------------------------------------------------------------------------------------------------|
.
.
.
|    81     |     0    | DEV_PRU_ICSSG0_CORE_CLK                                                                              | CLK_STATE_READY     | 225000000       |
|    81     |     1    | DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK                                     | CLK_STATE_READY     | 225000000       |
|    81     |     2    | DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK                                    | CLK_STATE_READY     | 333333333       |
|    81     |     3    | DEV_PRU_ICSSG0_IEP_CLK                                                                               | CLK_STATE_READY     | 225000000       |
|    81     |     4    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK                                     | CLK_STATE_READY     | 225000000       |
|    81     |     5    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK                                     | CLK_STATE_READY     | 200000000       |
|    81     |     6    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                     | CLK_STATE_READY     | 0               |
|    81     |     7    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                                              | CLK_STATE_READY     | 0               |
|    81     |     8    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                                            | CLK_STATE_READY     | 0               |
|    81     |     9    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                                | CLK_STATE_READY     | 0               |
|    81     |    10    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK                                      | CLK_STATE_READY     | 0               |
|    81     |    11    | DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                              | CLK_STATE_READY     | 500000000       |
|    81     |    12    | DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I                                                                      | CLK_STATE_READY     | 0               |
|    81     |    13    | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I                                                                      | CLK_STATE_READY     | 0               |
|    81     |    14    | DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I                                                                      | CLK_STATE_READY     | 0               |
|    81     |    15    | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I                                                                      | CLK_STATE_READY     | 0               |
|    81     |    16    | DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK                                                                     | CLK_STATE_READY     | 250000000       |
|    81     |    17    | DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK                                                                      | CLK_STATE_READY     | 50000000        |
|    81     |    18    | DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK                                                                       | CLK_STATE_READY     | 5000000         |
|    81     |    19    | DEV_PRU_ICSSG0_UCLK_CLK                                                                              | CLK_STATE_READY     | 192000000       |
|    81     |    20    | DEV_PRU_ICSSG0_VCLK_CLK                                                                              | CLK_STATE_READY     | 250000000       |
|    81     |    21    | DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O                                                                      | CLK_STATE_READY     | 0               |
|    81     |    22    | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O                                                                      | CLK_STATE_READY     | 0               |
|    81     |    23    | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O                                                                      | CLK_STATE_READY     | 0               |
|    82     |     0    | DEV_PRU_ICSSG1_CORE_CLK                                                                              | CLK_STATE_READY     | 225000000       |
|    82     |     1    | DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK                                     | CLK_STATE_READY     | 225000000       |
|    82     |     2    | DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK                                    | CLK_STATE_READY     | 333333333       |
|    82     |     3    | DEV_PRU_ICSSG1_IEP_CLK                                                                               | CLK_STATE_READY     | 225000000       |
|    82     |     4    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK                                     | CLK_STATE_READY     | 225000000       |
|    82     |     5    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK                                     | CLK_STATE_READY     | 200000000       |
|    82     |     6    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT                                     | CLK_STATE_READY     | 0               |
|    82     |     7    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT                                              | CLK_STATE_READY     | 0               |
|    82     |     8    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT                                            | CLK_STATE_READY     | 0               |
|    82     |     9    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT                                                | CLK_STATE_READY     | 0               |
|    82     |    10    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK                                      | CLK_STATE_READY     | 0               |
|    82     |    11    | DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK                              | CLK_STATE_READY     | 500000000       |
|    82     |    12    | DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I                                                                      | CLK_STATE_READY     | 0               |
|    82     |    13    | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I                                                                      | CLK_STATE_READY     | 0               |
|    82     |    14    | DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I                                                                      | CLK_STATE_READY     | 0               |
|    82     |    15    | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I                                                                      | CLK_STATE_READY     | 0               |
|    82     |    16    | DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK                                                                     | CLK_STATE_READY     | 250000000       |
|    82     |    17    | DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK                                                                      | CLK_STATE_READY     | 50000000        |
|    82     |    18    | DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK                                                                       | CLK_STATE_READY     | 5000000         |
|    82     |    19    | DEV_PRU_ICSSG1_UCLK_CLK                                                                              | CLK_STATE_READY     | 192000000       |
|    82     |    20    | DEV_PRU_ICSSG1_VCLK_CLK                                                                              | CLK_STATE_READY     | 250000000       |
|    82     |    21    | DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O                                                                      | CLK_STATE_READY     | 0               |
|    82     |    22    | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O                                                                      | CLK_STATE_READY     | 0               |
|    82     |    23    | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O                                                                      | CLK_STATE_READY     | 0               |

Regards,

Nick

0 xixiguohx 4 months ago in reply to Nick Saulnier

Intellectual 400 points

Hi Nick,

Thanks, this is very helpful. I tried add the related nodes like below, configure icssg1 to use 300Mhz from MAIN_2_HSDIVOUT0_CLK

icssg1_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 82 0>,   /* icssg1_core_clk */
						 <&k3_clks 82 20>;  /* icssg1_iclk */
					assigned-clocks = <&k3_clks 82 0>, <&icssg1_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 82 1>, <&k3_clks 82 0>;
					assigned-clock-rates = <300000000>, <0>;  /*300Mhz*/

And then I got these information on board,

root@p3y-kp:~# cat /sys/kernel/debug/clk/clk_summary 
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 clk:82:20                            0        0        0   250000000          0     0  50000
 clk:82:11                            0        0        0   500000000          0     0  50000
 clk:82:10                            0        0        0           0          0     0  50000
 clk:82:9                             0        0        0           0          0     0  50000
 clk:82:8                             0        0        0           0          0     0  50000
 clk:82:7                             0        0        0           0          0     0  50000
 clk:82:6                             0        0        0           0          0     0  50000
 clk:82:5                             0        0        0   200000000          0     0  50000
 clk:82:4                             0        0        0   225000000          0     0  50000
    clk:82:3                          0        0        0   225000000          0     0  50000
 clk:82:2                             0        0        0   333333333          0     0  50000
 clk:82:1                             0        0        0   225000000          0     0  50000
    clk:82:0                          0        0        0   300000000          0     0  50000
       30080000.icssg.coreclk-mux       0        0        0   300000000          0     0  50000
          30080000.icssg.iepclk-mux       0        0        0   300000000          0     0  50000

I think we got what we want.

But I did not understand "NOTE! At this point, I have not looked into whether there are tools to see if another part of the processor is using that clock source." What did you mean by another part of the processor?

Best Regards

xixiguo

0 xixiguohx 4 months ago in reply to xixiguohx

Intellectual 400 points

Hi Nick,

Thanks, this is very helpful. I tried add the related nodes like below, configure icssg1 to use 300Mhz from MAIN_2_HSDIVOUT0_CLK

icssg1_coreclk_mux: coreclk-mux@3c {
					reg = <0x3c>;
					#clock-cells = <0>;
					clocks = <&k3_clks 82 0>,   /* icssg1_core_clk */
						 <&k3_clks 82 20>;  /* icssg1_iclk */
					assigned-clocks = <&k3_clks 82 0>, <&icssg1_coreclk_mux>;
					assigned-clock-parents = <&k3_clks 82 1>, <&k3_clks 82 0>;
					assigned-clock-rates = <300000000>, <0>;  /*300Mhz*/

And then I got these information on board,

root@xx:~# cat /sys/kernel/debug/clk/clk_summary 
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 clk:82:20                            0        0        0   250000000          0     0  50000
 clk:82:11                            0        0        0   500000000          0     0  50000
 clk:82:10                            0        0        0           0          0     0  50000
 clk:82:9                             0        0        0           0          0     0  50000
 clk:82:8                             0        0        0           0          0     0  50000
 clk:82:7                             0        0        0           0          0     0  50000
 clk:82:6                             0        0        0           0          0     0  50000
 clk:82:5                             0        0        0   200000000          0     0  50000
 clk:82:4                             0        0        0   225000000          0     0  50000
    clk:82:3                          0        0        0   225000000          0     0  50000
 clk:82:2                             0        0        0   333333333          0     0  50000
 clk:82:1                             0        0        0   225000000          0     0  50000
    clk:82:0                          0        0        0   300000000          0     0  50000
       30080000.icssg.coreclk-mux       0        0        0   300000000          0     0  50000
          30080000.icssg.iepclk-mux       0        0        0   300000000          0     0  50000

I think we got what we want.

Best Regards

xixiguo

0 Nick Saulnier 4 months ago in reply to xixiguohx

TI__Mastermind 38830 points

Hello Xixiguo,

Thank you for testing this out! I will take this information and use it to fill out https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1049800/faq-pru_icssg-how-to-check-and-set-pru-core-frequency-in-linux later today.

Do I need to look for clocking conflicts after changing a PLL output?

Short answer:
For AM64x PRU Core clock frequency, you do NOT need to check for clocking conflicts unless you are using OBSCLK0 output with MAIN_PLL2_HSDIV0_CLKOUT as the clock source. (the clock sources with adjustable frequencies do not source any other peripherals). However, if you are setting clock frequencies for other clock inputs, you SHOULD check for clocking conflicts.

More details:
Some clock sources can provide a clock to multiple peripherals within a device. For example, MAIN_PLL0_HSDIV6_CLKOUT (200 or 250 MHz) can be used to source ICSSG IEP clock, but it can also source the GTC, the main domain CPTS, the CPSW CPTS, and the PCIE CPTS. So if you set a specific clock frequency for MAIN_PLL0_HSDIV6_CLKOUT with assigned-clock-rates, then you should check whether any of those other peripherals are using MAIN_PLL0_HSDIV6_CLKOUT, and make sure that you are not trying to set MAIN_PLL0_HSDIV6_CLKOUT to different frequencies in different device tree nodes.

How to check for clocking conflicts?

At this point in time, I do not have a super easy way to do this. (any future readers, if you have better answers feel free to write them down). We are planning to release a Clock Tree Tool for AM64x later this year (tentatively February 2022), but it is not currently available. Here is the cleanest method I found so far:

1) Find the name of the clock source in the TISCI documentation at https://downloads.ti.com/tisci/esd/latest/5_soc_doc/am64x/clocks.html

2) Find all the peripherals that can use that clock source

3) use the kernel clk_summary to check existing clock settings from the terminal

Let's take the example of MAIN_PLL0_HSDIV6_CLKOUT:

1) MAIN_PLL0_HSDIV6_CLKOUT is named MAIN_0_HSDIVOUT6_CLK at https://downloads.ti.com/tisci/esd/latest/5_soc_doc/am64x/clocks.html

2) By using Ctrl-f, I see that MAIN_0_HSDIVOUT6_CLK is used by:
AM64X_DEV_CPSW0 (ID = 13) - entry 3
AM64X_DEV_CPTS0 (ID = 84) - entry 2
AM64X_DEV_GTC0 (ID = 61) - entry 2
AM64X_DEV_PCIE0 (ID = 114) - entry 3
AM64X_DEV_PRU_ICSSG0 (ID = 81) - entry 5
AM64X_DEV_PRU_ICSSG1 (ID = 82) - entry 5

3) Now I can run
# cat /sys/kernel/debug/clk/clk_summary
and see if any of these are used:
clk:13:3
clk:84:2
etc.

Regards,

Nick

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RE: AM6442: How to check and set the PRU core frequency in Linux?