Trying to understand the boot process from reading the TRM.
Is it the R5 or the A53 that boots from the boot memories?
(This is unclear to me?)
Section 4.7 describes the image loaded from the OSPI interface as:
"The image data (blob) is considered simply as a byte stream. On devices that are multiple bytes wide (for
example, PCIe) the image must be formatted so that all multi-byte fields match the endianness of the device.
The MCU will always run in little endian mode."
This seems insufficient to figure out what needs to live in the OSPI flash to make boot work.
Where does this code get loaded? IE If im building an image to live here, what is my origin address?
Is this loaded in on board SRAM, executed in place?
Where does the execution start address come from?
Trying to get a bare metal A53 running...
