DRA821U: Min/Max time at Power up/down sequence

The timing tolerance is +/- 5% from min/max for each time step of the power up & down sequence.

Hi Bill

So, I'd like to explain my question again to clear enough.

Data manual says that

Does the above mean,

   T0:   min 0ms                  ~  max 0ms

   T1:   min (0.5*0.95) ms   ~   max (0,5*1.05) ms

   T2:   min (1.0*0.95) ms   ~   max (1.0*1.05) ms 

   T3:   min (1.5*0.95) ms   ~   max (1.5*1.05) ms

   T4:   min (11*0.95) ms   ~   max (11*1.05) ms 

Does it correct?

Yes

Q1) Yes, elapsed time tolerance is +5% as stated earlier. Your system timing can be longer if your initial system power up time to 1st operation total elapsed time criteria (i.e. system CAN communications) is met.  

Q2) There is no max power supply rise time spec but it should be included in overall elapsed time between power up steps.

Q3) Time stamps can be viewed as min for the TI power components used in recommended SoC power solutions. They are shown for reference to describe  an optimized power up & down seq performance. An uncontrolled lost of power event (battery failure or removal) is the most demanding event to support. The DM power down time stamps show how to begin disabling the SoC high current loads (VDD_CORE & VDD_CPU) as soon as possible so that the decoupling cap charge can be discharged as quickly as possible. The goal is to reduce supply levels below SoC Vmin (0.3V per DM). The TI PMIC & Buck converters used to supply these rails have active discharge FET feature which improves discharge performance.

You can be longer if you never expect to have an uncontrolled power down event. This means your system design will ensure the input power to SoC power stage will always remain above Vin min during the entire power down seq elapsed time.y

Q4) No max fall time is specified for SoC supply slopes.  Be aware that your system power cycling and any functional safety checks might impose a max discharge time but that is dependent on your system requirements and not the SoC.