I am implementing DDR3 on an AM5729 and I would like to run HyperLynx SI DDRx Wizard on my board design. The DDRx wizard requires a timing model for the DDR3 controller to provide min/max skew between CLK and ADDR/CMD/CTL signals, CLK to DQS, DQS to DQ, and DQS to DM, as well as setup and hold time for reads. I would expect this information to be somewhere in the datasheet or the technical reference manual, but I cannout find it. Where can I find this information? I cannot run the signal integrity simulation without it. The parameters I need to know are
Thanks in advance.