Hi
Some questions about the DDR3A interface, and descriptions from SPRUHN7C document:
- Is there a way to change the DDR3CLKOUP output drive and slew rate ?
- Is the ACIOCR register operational ? how can we use it ? are there constraints about when to change the <31-30> bit values (before leveling? after leveling ? else?
- same kind of question about ZQnCR0 register :
- How to use ZDATA feature ?
- we tried to force the same ZDATA values as the ones automatically retrieved from levelling in ZQnSR0 register , but this makes the core to crush.
- to which impedance traces are related ZQ0CR0 , ZQ1CR0,ZQ2CR0, and ZQ3CR0 ?
With best regards,
Bruno
