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[FAQ] DRA821U: How to use DDR BIST engine for filling up pattern.

Part Number: DRA821U
Other Parts Discussed in Thread: TEST, DRA821, TDA4

Dear support,

For DDR ECC per-load, we use the BIST engine for SDRAM initilization, but it fails, the following is the registers configured,

Could you help me check whether the configuration is Ok?

I want to initialize the 0x9000 0000 ~ 0x9000 03FF(1KB)

/* BIST start address 0.*/
Tst_DDR_CTL->DENALI_CTL_196 = 0x90000000;
/* BIST start address 1.*/
Tst_DDR_CTL->DENALI_CTL_197 = 0x00000000;
/* BIST test mode.*/
/* 4 - memory initialization. */
Tst_DDR_CTL->DENALI_CTL_200 = 0x4;
/* BIST data pattern 0.*/
Tst_DDR_CTL->DENALI_CTL_201 = 0x55AA55AA;
/* BIST data pattern 1.*/
Tst_DDR_CTL->DENALI_CTL_202 = 0x55AA55AA;
/* BIST data pattern 2.*/
Tst_DDR_CTL->DENALI_CTL_203 = 0x55AA55AA;
/* BIST data pattern 3.*/
Tst_DDR_CTL->DENALI_CTL_204 = 0x55AA55AA;

/* bit0 -BIST GO */
/* bit18 -21, the number of address bits during BIST operation. */
/* 9 - represent 1KB .*/
Tst_DDR_CTL->DENALI_CTL_194 |= 0x90001;

  • Hi,

    Sorry for the late reply. This code looks to be fine. Are you seeing it working fine? Any specific reason for using BIST module to initialize DDR? You could even use DMA to initialize DDR.

    We have used DMA to initialize/prime DDR. You could find this code in ti-processor-sdk-rtos-j721e-evm-08_01_00_11/pdk_jacinto_08_01_00_33/packages/ti/board/src/j721e_evm/board_ddr_prime_dma.c file. 

    Regards,

    Brijesh

  • Hi,

    It didn't work, and the address 0x9000 0000 ~ 0x9000 03FF is not filled with expected value(0x55AA55AA).

    Is there any demo code for BIST engine?

    For DMA to initilize DDR, is it faster than BIST engine?

  • Hi Yu Kui,

    Could you please help me understand the reason for filling up only 1024 bytes? 

    Unfortunately, SDK does not have demo code for using BIST for filling up memory. I had tried it earlier using gel files, it worked fine. 

    Depending on the usecase, it might be better to use DMA engine.

    Regards,

    Brijesh

  • Hi Brijesh

    I want to use BIST engine for DDR pre-looading when inline ECC is enabled. As for 1024 bytes, it is just a demo to verify that BIST engine works fine or not.

    Thank you in advance! 

  • Hi Yu Kui,

    Yes, we could use BIST engine, but the pattern must be 0x0. We cannot write any other pattern. Also the speed will be similar to what DMA can write. This is why i was suggesting to use DMA.. I am not sure why DMA is not used for pattern filling. Could you please help me understand the reason? 

    Regards,

    Brijesh

  • Hi, Brijesh

    TI supporter in china suggestted we can use the BIST emgine for DDR pre-loading.

    And I will tried to use pattern with zero, then I will response it worlks or not.

    One more question for BIST engine:

    How to know the BIST engine successfully complete the DDR pre-loading?via DDRSS_CTL_194 bit8(data check status)? Should I need to poll bit8 as 1?

    In the demo configuration with filling pattern 0x55AA55AA, the DDRSS_CTL_194 bit8 is 1.

  • Hi Yu Kui,

    You could use bit11 in DDRSS_CTL_293 register to wait for completion. 

    Regards,

    Brijesh

  • Hi Yu Kui,

    Please use below code to use BIST function to fill pattern in DDR. Please use fill pattern to 0x0 for ECC to work correctly. 

    /***********************macro define************************/
    #define DDR_START_ADDR 0x80000000
    #define DDR_SIZE 32
    #define DDR_DATA 0x11111111
    #define DDR_DATA1 0xAAAAAAAA
    #define DDR_DATA2 0x55555555
    #define DDR_DATA3 0xFFFFFFFF

    #define J7ES_DDR_SS_BASE_MCUStart 0x02990000U
    #define DDRSS_CTL_194__SFR_OFFS 0x308
    #define DDRSS_CTL_195__SFR_OFFS 0x30c
    #define DDRSS_CTL_196__SFR_OFFS 0x310
    #define DDRSS_CTL_200__SFR_OFFS 0x320
    #define DDRSS_CTL_201__SFR_OFFS 0x324
    #define DDRSS_CTL_202__SFR_OFFS 0x328
    #define DDRSS_CTL_203__SFR_OFFS 0x32c
    #define DDRSS_CTL_204__SFR_OFFS 0x330
    #define DDRSS_CTL_293__SFR_OFFS 0x494
    #define DDRSS_CTL_295__SFR_OFFS 0x49c

    Board_STATUS fillTestPattern()
    {
    Board_STATUS status = BOARD_SOK;


    BOARD_DEBUG_LOG("Start DDR pattern test!\r\n");
    // Define start address
    HW_WR_REG32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_196__SFR_OFFS, (DDR_START_ADDR - 0x80000000));
    // Define memory size
    HW_WR_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_194__SFR_OFFS, 63 << 16, 16, DDR_SIZE);
    // Enable data check
    HW_WR_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_194__SFR_OFFS, 1 << 24, 24, 1);
    // Disable addr check
    HW_WR_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_195__SFR_OFFS, 1, 0, 0);
    // Set BIST Mode to Mem Init
    HW_WR_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_200__SFR_OFFS, 7, 0, 4);
    // Set Data Patterns
    HW_WR_REG32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_201__SFR_OFFS, DDR_DATA);
    HW_WR_REG32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_202__SFR_OFFS, DDR_DATA1);
    HW_WR_REG32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_203__SFR_OFFS, DDR_DATA2);
    HW_WR_REG32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_204__SFR_OFFS, DDR_DATA3);
    // Clear Interrupt
    HW_WR_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_295__SFR_OFFS, 1 << 11, 11, 1);
    // Trigger Write
    HW_WR_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_194__SFR_OFFS, 1, 0, 1);
    // Wait for Finish
    while(HW_RD_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_293__SFR_OFFS, 1 << 11, 11) !=1) BOARD_DEBUG_LOG("keep waiting finish!\r\n");

    // Clear Interrupt

    HW_WR_FIELD32_RAW(J7ES_DDR_SS_BASE_MCUStart + DDRSS_CTL_295__SFR_OFFS, 1 << 11, 11, 1);

    }

    Regards,

    Brijesh

  • Hello, Brijesh

    I tired the code above, it seems successfully initialize the specified memory space as 0. But the bit11 in DDRSS_CTL_293 is not set, then the program will stuck in the while loop.

    Memlay_MemSet64((uint64*)0x90000000, 0x01uLL, 0x400uLL);

    /* BIST start address 0.*/
    Tst_DDR_CTL->DENALI_CTL_196 = 0x90000000 - 0x80000000;
    /* BIST initialization size, 1K. */
    Tst_DDR_CTL->DENALI_CTL_194 |= 0xA0000;
    /* BIST enable data check. */
    Tst_DDR_CTL->DENALI_CTL_194 |= 0x1000000;
    /* BIST disable address check. */
    Tst_DDR_CTL->DENALI_CTL_195 |= 0x1;
    /* BIST start address 1.*/
    Tst_DDR_CTL->DENALI_CTL_197 = 0x00000000;
    /* BIST test mode.*/
    /* 4 - memory initialization. */
    Tst_DDR_CTL->DENALI_CTL_200 = 0x4;
    /* BIST data pattern 0.*/
    Tst_DDR_CTL->DENALI_CTL_201 = 0x00;
    /* BIST data pattern 1.*/
    Tst_DDR_CTL->DENALI_CTL_202 = 0x00;
    /* BIST data pattern 2.*/
    Tst_DDR_CTL->DENALI_CTL_203 = 0x00;
    /* BIST data pattern 3.*/
    Tst_DDR_CTL->DENALI_CTL_204 = 0x00;
    /* BIST clear interrupt. */
    Tst_DDR_CTL->DENALI_CTL_295 = 0x800;

    /* bit0 -BIST GO */
    /* bit18 -21, the number of address bits during BIST operation. */
    /* 9 - represent 1KB .*/
    Tst_DDR_CTL->DENALI_CTL_194 |= 0x1;

    while(((Tst_DDR_CTL->DENALI_CTL_293) & 0x800) != 0x800)

    /* BIST clear interrupt. */
    Tst_DDR_CTL->DENALI_CTL_295 = 0x800;

  • Hi Yu Kui,

    I used this code on TDA4xVM, may be there are some changes required for DRA821. Can you please see if there is any other bit in the controller which can be polled for BIST completion?

    Regards,

    Brijesh

  • Hello, Brijesh

    I compare the DDRSS_CTL_293 register between DRA821 and TDA4XVM, and the descriptions are the same.

    And I go through the DRA821 TRM, there is none bit which can be polled for BIST completion.

    TDA4:

    DRA821: