AM6548: R5 Cores Cache coherency

Sanjay TR

Prodigy 35 points

Part Number: AM6548

Hi,

TI RTOS is running on R5F0 and R5F1 cores which are configured to run in Split Mode.

Some Data is written into MCU_MSRAM from R5F0 and we are trying to read the same location from R5F1.But the data looks different on both cores.
We have a structure in MCU_MSRAM. It is filled partially from R5F0 and from R5F1. After filling data, we memcpy this structure from MCU_MSRAM to DDR from R5F0. After memcpy , on reading the DDR, data written from R5F1 is inconsistent.

We suspect Cores Cache coherency on this issue.

Is there a way to ensures data consistency?

Thanks

Sanjay

over 2 years ago

0 Karan Saxena over 2 years ago

TI__Guru* 75182 points

Hi Sanjay,

The R5F cores are not cache coherent, any update you make from one R5F to a cacheable memory will modify the contents of the cache they will only show up in the underlying memory when that block is evicted from the cache and contents are written back to memory.

1. If the structure needs to be asynchronously updated by both the R5Fs then you should allocate that in a non-cacheable memory wrt both the R5Fs.

2. In case the writes are not asynchronous and more sequential, you could do an explicit cache write back when you write from one core and invalidate on the other core before reading.

Regards

Karan

0 Dhruva Krishnadas over 2 years ago in reply to Karan Saxena

Intellectual 410 points

Hi Karan,

Our R5F cores are working independently, however they are synchronized through the use of RPMsgs. R5F0 signals the R5F1 whenever needed.

In this case, how could we adopt strategy 2 and perform an explicit cache write back from each core?

0 Karan Saxena over 2 years ago in reply to Dhruva Krishnadas

TI__Guru* 75182 points

Hi Dhruva,

You can use the below reference code:

1. Write back: https://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/drv/udma/examples/udma_memcpy_test/udma_memcpy_test.c#n321

Write back the contents after they have been written from the writer core. This will make sure the underlying memory has the latest contens.

2. Invalidate: https://git.ti.com/cgit/processor-sdk/pdk/tree/packages/ti/drv/udma/examples/udma_memcpy_test/udma_memcpy_test.c#n446

Invalidate from reader core. This will make sure that the reader core is not reading stale contents from its cache but fetching the fresh contents from the memory.

Regards

Karan

0 Chris Yorkey over 2 years ago in reply to Karan Saxena

TI__Genius 14715 points

Team,

I believe Sanjay and team are satisfied with the responses here.

Please advise if otherwise but I am going to suggest that TI Thinks Resolved.

Regards,

Chris

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AM6548: R5 Cores Cache coherency