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TMS320C6747: PLL doesn't work correctly after enabled PLLEN bit

Cameron Wutzke
Intellectual 1991 points
Part Number: TMS320C6747

Hello experts! 

We have an issue where the TMS320C6747 couldn’t boot from initial PLL setting function in the bootloader and it looks PLL doesn’t work correctly after enabling PLLEN bit. I would love to hear thoughts if incorrectly setting bits could have damaged some units.

We missed the CLKMODE setting as internal oscillation with crystal (set as 0), but actually we supply the 24MHz with external oscillator with 1.2V. – must be set as “1”. Could we have damaged the PLL block internally? Even though we corrected the CLKMODE to 1, the PCBA’s DSP doesn’t boot– change the PLLEN from Bypass mode to PLL mode (set 0 to 1). So my concern is that internal PLL block may be broken with wrong setting of CLKMODE. The Error message is below and outputs continuously:

 

C674X_0: Trouble Halting Target CPU: (Error -2062 @ 0x0) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.73.0)

C674X_0: Encountered Illegal Op-code

 

Any thoughts? Please note that good PCBs works well, but bad PCBs have same problem.

Thank you!

  • +1
    TI__Guru 55265 points

    The device was designed to power-up and execute code with either type of reference clock source. We recommend changing the CLKMODE bit from its default state of "0" to "1" when using 1.2V square wave source before configuring the PLL. This recommendation is simply placing the device in a more optimized mode of operation, but forgetting to change the bit should not damage the device.

    I suspect you have a marginal system issue, where some PCB assemblies operate as expected. You should confirm all power sources are operating within their valid operating ranges. Make sure the supplies are stable and do not have too much noise. Check your clock source to confirm it is providing a valid reference clock. Compare power supply and other signal measurements between working PCBs and non-working PCBs to see if you spot any obvious differences. Make sure your PCB assembly vendor did not accidently install wrong component values on some PCBs.

    Have you confirmed your software is configuring the correct PLL multiplier and divider values based on your 24 MHz reference clock frequency?

    Regards,
    Paul