Other Parts Discussed in Thread: STRIKE
Hi experts,
My customer wants to deal with errata (ESD countermeasures). When supplying 1.8V from a 3.3V oscillator with a resistive divider, they think it will be difficult to achieve a rise and fall of less than 5ns with a resistive divider. It would be nice if they had an oscillator to supply at 1.8V, but they don't at the moment.
Q1:If it is not possible to achieve less than 5ns, could you tell me what kind of impact it is expected to have on operation?
Quoted from "2.1.4 System-Level ESD Immunity Usage Note
On all silicon revisions, certain design elements make this device susceptible to radiated noise during an ESD strike, as described in the standard IEC 61000-4-2. Exposure to the electrical noise caused by the ESD can cause soft device failures due to noise coupling on the system clock (OSCIN). ESD events within the IEC spec range do not cause permanent device damage and full functionality is recoverable with a device reset. The sensitivity to this noise issue is primarily due to the 1.2V oscillator/clock input implemented on this device. The low voltage range, coupled with slow rise and fall times, provides a lower noise margin than other TI devices with higher voltage internal oscillators (for example, 1.8V or 3.3V oscillators).
If ESD robustness is a concern, it is strongly recommended to avoid using the internal oscillator as a clock source. An external 3.3V clock source with a resistor voltage divider as in Figure 2 can be used to externally generate the required 1.2V input clock. By using an external clock input with fast rise/fall times (less than 5 ns), the noise margin improves significantly, increasing ESD noise resistance.
Q2:Also, when connecting an oscillator, is it OK to connect the OSCVSS pin to the GND of PLL0 and PLL1_VSSA?
In the "OMAP-L13x / C674x / AM1x schematic review guidelines", it was classified as "Analog ground nodes", so please let me confirm this just in case.
Best regards,
O.H