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AM1802: ESD countermeasures

Genius 5675 points
Part Number: AM1802
Other Parts Discussed in Thread: STRIKE

Hi experts,

My customer wants to deal with errata (ESD countermeasures). When supplying 1.8V from a 3.3V oscillator with a resistive divider, they think it will be difficult to achieve a rise and fall of less than 5ns with a resistive divider. It would be nice if they had an oscillator to supply at 1.8V, but they don't at the moment.

Q1:If it is not possible to achieve less than 5ns, could you tell me what kind of impact it is expected to have on operation?

Quoted from "2.1.4 System-Level ESD Immunity Usage Note

On all silicon revisions, certain design elements make this device susceptible to radiated noise during an ESD strike, as described in the standard IEC 61000-4-2. Exposure to the electrical noise caused by the ESD can cause soft device failures due to noise coupling on the system clock (OSCIN). ESD events within the IEC spec range do not cause permanent device damage and full functionality is recoverable with a device reset. The sensitivity to this noise issue is primarily due to the 1.2V oscillator/clock input implemented on this device. The low voltage range, coupled with slow rise and fall times, provides a lower noise margin than other TI devices with higher voltage internal oscillators (for example, 1.8V or 3.3V oscillators).

If ESD robustness is a concern, it is strongly recommended to avoid using the internal oscillator as a clock source. An external 3.3V clock source with a resistor voltage divider as in Figure 2 can be used to externally generate the required 1.2V input clock. By using an external clock input with fast rise/fall times (less than 5 ns), the noise margin improves significantly, increasing ESD noise resistance.

Q2:Also, when connecting an oscillator, is it OK to connect the OSCVSS pin to the GND of PLL0 and PLL1_VSSA?

In the "OMAP-L13x / C674x / AM1x schematic review guidelines", it was classified as "Analog ground nodes", so please let me confirm this just in case.

Best regards,
O.H

  • A1: A fast rise/fall time on the reference clock makes it difficult for noise to couple into OSCIN. The chance of noise coupling into OCSIN is a function of the reference clock rise/fall time, the specific system design, and the electrical noise environment. Even a reference clock with less than 5ns rise/fall time may not prevent noise from coupling into OSCIN when exposed to extreme electrical noise. The 5ns limit was chosen because it is a value which should be easy to achieve and has proven to be successful with a few systems that were experiencing noise susceptibility issues. The internal reference clock may be glitched if enough noise couples on the reference clock signal and causes the OSCIN input buffer to see a non-monotonic transition. If this occurs, the glitch on the internal reference clock may over-clock digital circuits in the device. Over-clocking has a good chance of causing these circuits to do very unpredictable things.

    A2: The datasheet recommends separate low pass filters for PLL0 and PLL1, so it is not clear how you would connect the OSCVSS pin to the same ground as PLL0 and PLL1 since they each have their own grounds after their respective filter. OSCVSS should be connected to the same digital ground as the reference clock source.

    Regards,
    Paul

  • I forgot to address the comment about not being able to achieve a 5ns rise/fall. 

    Most LVCMOS oscillators define their rise/fall time based on the worst case capacitive load, which is typically much larger than the OSCIN input capacitance. So this is not typically a problem as long as they do not use a high impedance voltage divider.

    They may need to test a few solutions while connected to OSCIN, by measuring the actual rise/fall time as close as possible to the OSCIN pin using a low capacitance FET scope probe.

    Regards,
    Paul

  • Hi Paul,

    Thank you for your reply. I understood.

    We will contact the customer to check the product on an actual working basis, and we will contact you again if there are any real problems or additional questions.

    Best regards,
    O.H