Hi,
I want to use the L2 memory of AM5718 MPU (cortex-a15) as SRAM.
I think that the L2 memory area can be divided into Data RAM by changing the setting of the L2 control register (see Arm Cortex-A15 TRM Revision: r4p0 4.3.48 L2 control register), but in AM5718 TRM(SPRUHZ7I) I can't find a way to use the MPU's L2 control register.
Is the L2 memory of AM5718-HIREL MPU available only for cache?
Thanks for your help.