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AM5718: How to use MPU L2 memory as SRAM

Part Number: AM5718


I want to use the L2 memory of AM5718 MPU (cortex-a15) as SRAM.

I think that the L2 memory area can be divided into Data RAM by changing the setting of the L2 control register (see Arm Cortex-A15 TRM Revision: r4p0 4.3.48 L2 control register), but in AM5718 TRM(SPRUHZ7I) I can't find a way to use the MPU's L2 control register.

Is the L2 memory of AM5718-HIREL MPU available only for cache?

Thanks for your help.

  • Hello,

    The Cortex-A15's L2 cache cannot be configured to be used as a SRAM. The L2 cache for the A15 does have some vendor configurable options and the L2CTRL register described in 4.3.48 describes those options in integrating in backing memories. These options are setup by our ROM code to match the TI implementation.  Only in the event of an errata would later SW ever write to these, and it would have to happen via a SMC call.

    You are correct that some TI processes like the C6x and C7x DSPs do allow caches to be reconfigured as SRAMs but that is not the case for the Cortex-A15.


    Richard W.