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TDA3MV: TDA3MV: MCAN PLL - jitter quantification

Andre4234
Intellectual 780 points
Part Number: TDA3MV

Hello, 

which external clock input, and which internal PLLs are involved to create the timing of the external CAN-FD signals (FCLK, MCAN_CLK)? 

I'm interested in calculating the overall jitter for the CAN-FD protocol. The jitter is a combination of 
- ext. clock source (oscillator) jitter, 
- plus the jitter of the internal PLLs (while they are accelerating/decelerating, to chase their input clock phase). 

What is the overall jitter contribution from the internal PLLs, which impact the ext. CAN-FD signal timing? 

Thanks and best regards, 
Andre. 

  • 0
    TI__Mastermind 46692 points

    Andre,  As was highlighted in email:

    Our char results across 13-bit-time shows:   

    The jitter measured at n-cycle (n=206) => STDev of 112.8ps and a Peak to peak of 1.22 ns.

    TIE ranged from 300ps at room temp to 450 at room temp on a strong and nominal device respectively.

    Both results indicate we are well within tolerance of max phase margin of 10.4 ns AT 5mbps.   

    The CAN-FD spec states that a maximum osc tolerance of 1.58 percent is supported, but to support  this several system level assumptions need to be made – in the case of 1.58% the max rate supported is 125kb.  Other customer specific system level factors  also influence the maximum allowed tolerance.

    The TDA3x datasheet recommends that the primary oscillator inputs has an accuracy of 200 ppm (or 50 ppm if RGMII is used)

    Regards,

    Kyle