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AM5726: AM5726: PCIe hot-reset support

Part Number: AM5726


I am trying to determine if the AM5726 supports PCIe hot-reset for the following use case of setting up PCIe lanes for an FPGA that is booted from user-space. At the time the kernel initializes the PCIe interfaces, the FPGA is not yet booted. We would like to do such from user-space, and then have PCIe "re-learn" the bus members so that the FPGA is found.

In the AM572X TRM (Silicon revision 2.0, 1.1) I have found the following in PCIe Standard Specific Resets to the PCIe Core Logic

PCIe hot-reset condition - As defined by the PCIe standard: reset condition propagated in-band (over
the PCIe wire) from an upstream port to a downstream port, using the TS1 and TS2 OS (see the PCI
Express Base 3.0 Specification, revision 1.0). Requires the link to be already powered and up. The hot
reset causes the link to go down and up again, causing a link-down reset condition, and as such is a
fundamental reset.
The hot reset sequence can be tracked in the LTSSM by the transition to "hot reset" state, then on to
"detect" and the rest of the link-up sequence.
• When RC, a hot reset is generated by writing the bit “Secondary Bus Reset” of the PCIe standard
“Bridge Control Register” - BRIDGE_INT [22] SEC_BUS_RST bit .
• When EP, a host reset is automatically processed by the controller hardware.

However, I don't see any support for this in the pci-dra7xx.c controller driver. 

Is this possible at all?

Thank you in advance

  • I have observed that after writing the BRIDGE_INT [22] SEC_BUS_RST bit, the LTSSM never leaves the HOT_RESET (0x1F) state. 

    devmem2 0x5100003c w 0x004101A6
    /dev/mem opened.
    Memory mapped at address 0xb6f64000.
    Read at address 0x5100003C (0xb6f6403c): 0x000101A6
    Write at address 0x5100003C (0xb6f6403c): 0x004101A6, readback 0x004101A6

    devmem2 0x51002104
    /dev/mem opened.
    Memory mapped at address 0xb6f6d000.
    Read at address 0x51002104 (0xb6f6d104): 0x0000007D

  • I was able to get back to state L0 by clearing BRIDGE_INT [22] SEC_BUS_RST and setting LTSSM_EN in PCIECTRL_TI_CONF_DEVICE_CMD

    devmem2 0x5100003c w 0x000101A6
    /dev/mem opened.
    Memory mapped at address 0xb6f03000.
    Read at address 0x5100003C (0xb6f0303c): 0x000001FF
    Write at address 0x5100003C (0xb6f0303c): 0x000101A6, readback 0x000101A6

    devmem2 0x51002104 w 0x1
    /dev/mem opened.
    Memory mapped at address 0xb6ff5000.
    Read at address 0x51002104 (0xb6ff5104): 0x00000000
    Write at address 0x51002104 (0xb6ff5104): 0x00000001, readback 0x00000001

    devmem2 0x51002104
    /dev/mem opened.
    Memory mapped at address 0xb6f0e000.
    Read at address 0x51002104 (0xb6f0e104): 0x00000045