Hello
I am trying to determine if the AM5726 supports PCIe hot-reset for the following use case of setting up PCIe lanes for an FPGA that is booted from user-space. At the time the kernel initializes the PCIe interfaces, the FPGA is not yet booted. We would like to do such from user-space, and then have PCIe "re-learn" the bus members so that the FPGA is found.
In the AM572X TRM (Silicon revision 2.0, 1.1) I have found the following in
24.9.4.4.2.2 PCIe Standard Specific Resets to the PCIe Core Logic
PCIe hot-reset condition - As defined by the PCIe standard: reset condition propagated in-band (over
the PCIe wire) from an upstream port to a downstream port, using the TS1 and TS2 OS (see the PCI
Express Base 3.0 Specification, revision 1.0). Requires the link to be already powered and up. The hot
reset causes the link to go down and up again, causing a link-down reset condition, and as such is a
fundamental reset.
The hot reset sequence can be tracked in the LTSSM by the transition to "hot reset" state, then on to
"detect" and the rest of the link-up sequence.
• When RC, a hot reset is generated by writing the bit “Secondary Bus Reset” of the PCIe standard
“Bridge Control Register” - BRIDGE_INT [22] SEC_BUS_RST bit .
• When EP, a host reset is automatically processed by the controller hardware.
However, I don't see any support for this in the pci-dra7xx.c controller driver.
Is this possible at all?
Thank you in advance