DRA76P: can ti RTOS support cache flush for a certain address for tda2/dra76x

customer have video processing issues on DRA762/TDA2, 

when use VPE to process video data, vide data in buffer will be cached, after using hardware accelerate feature，parts of data in the cache is not flushed to data buffer,

question:

      1. is there any API in PDK to flush data cache by manual, when there has new data update in cache, flush it to data buffer by manual

      2. if vide data in data buffer is cached,  VPE enable HW acceleration function, is it possible that data update in CACHE not flush to DDR? if yes, is there any method to avoid

Thanks