AM6442: Ethercat SoC and PHY clocking advice

I'm not an Ethercat expert, but a common clock source is desired to reduce jitter in time-synchronized packets used to initiate events in down-stream devices. 

A common clock source is desired because it is not possible to purchase multiple clock sources that produce an exact frequency. Each clock source has a combined frequency error associated with three major contributors. The largest contribution to error is the initial accuracy of the resonator within the clock source, where the most common is an AT-cut quartz crystal. You can buy low PPM error clock sources, but it is not possible to buy a clock source with an error of 0PPM. Another contributor is frequency change with respect to operating temperature change. You can buy expensive oven controlled clock sources which provide very minimum frequency drift relative to operating environment, but again it is not possible to buy one with an error of 0PPM. Another contribution to error is aging of the resonator.

Portions of your system would be operating a few PPM faster or slower relative to each other when using multiple clock sources in the system. This is problematic as data must flow through synchronizers when crossing in and out of clocking domains.  This creates jitter in the data path. Therefore, it is desirable to use a common clock source for each device in the path of Ethercat data and the processing of time-sync packets. Note: This doesn't completely eliminate the possibility of jitter, it simply reduces the probability of it occurring.

The AM64x device has internal PLLs that are used to clock most of the internal circuits. These PLLs are always increasing and decreasing in frequency as necessary to maintain a lock to the applied 25MHz reference clock. So the PLLs will inject a certain amount of jitter. It is not clear which of the clocking options is best for your system. There are many system dependencies which must be considered and it is not possible for TI to understand all of these dependencies and make a clear cut recommendation. For example, will the PHY you select operate as expected if you use our PLL based clock output as the source for your Ethernet PHYs.  Note: We can not define the jitter profile of our clock outputs because this is also system dependent. Many things can impact the jitter profile of our internal PLLs, like the jitter of the 25MHz reference clock, power supply noise, electrical noise of the environment, etc. Therefore, the system designer needs to understand all of these dependencies and interactions when select the best clocking option for their system.

Regards,
Paul

From my understanding, there is a system level test performed by connecting several Ethercat devices together and configuring each device to create a periodic pulse. A scope is used to measure the alignment of each pulse relative to the others over a long period of time by turning on persistence in the scope. This will show how much jitter is introduced by each device connected in the system. Using a common clock is one way to improve the jitter introduced by the device in question. 

My knowledge of this topic is limited to what I have learned while answering other customer questions. Hopefully, you can find some good white papers or application notes to help you with your system development.

Regards,
Paul