PROCESSOR-SDK-AM64X: GPIO INTERRUPT CONFIG IN AM64x MCU+ SDK 08.01.00

Hi HieuTa,

Hieu Ta said:

but I have a ERROR when running

I'm unable to reproduce this failure. Did you follow all the EVM setup instructions? Please see:

• https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/EVM_SETUP_PAGE.html#autotoc_md21
• https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/EVM_SETUP_PAGE.html#EVM_FLASH_SOC_INIT

Hieu Ta said:

I not understanding intrNum = CSLR_R5FSS0_CORE0_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8 from?

This is the R5FSS VIM interrupt number (40) connected to the GPIOMUX_INTRTR0 Output #8, please see the TRM, Section 9.3.2.2 GPIOMUX_INTRTR0 Integration.

I have provided many details here: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1068969/lp-am243-gpio-interrupt-config

The situation is a bit different for MCU GPIO.

MCU_GPIO0_10 maps to BANK interrupt (10/16) = 0

See the TRM:

• Figure 12-56. MCU_GPIO0 Integration : MCU_GPIO_BANK0_INT -> MCU_GPIOMUX_INTRTR0 MCU_GPIO_INTRTR_IN_30
• 9.3.2.1 MCU_GPIOMUX_INTRTR0 Integration : MCU_GPIOMUX_INTRTR0 MCU_MCU_GPIOMUX_INTROUTER0_OUTP_[3:0] -> R5FSS0_CORE0/1 R5FSS0_CORE0/1_INTR_IN_[107:104]

By default, these MCU_GPIOMUX_INTRTR0 Outputs are allocated to the A53, not to the R5Fs. Thus, the Resource Management Board Configuration must updated. Please see: 

• https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/RESOURCE_ALLOCATION_GUIDE.html
• https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/TOOLS_SYSFW.html#BOARCFG_GEN

For example, change this:

{
    .num_resource = 4,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    .start_resource = 0,
    .host_id = TISCI_HOST_ID_A53_2,
},

to this:

{
    .num_resource = 4,
    .type = TISCI_RESASG_UTYPE (TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),
    .start_resource = 0,
    .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
},

Now, the parameters for can be updated as shown in the code below:

rmIrqReq.valid_params           = 0U;
rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
rmIrqReq.global_event           = 0U;
rmIrqReq.src_id                 = TISCI_DEV_MCU_GPIO0;
rmIrqReq.dst_id                 = TISCI_DEV_R5FSS0_CORE0;
rmIrqReq.ia_id                  = 0U;
rmIrqReq.vint                   = 0U;
rmIrqReq.vint_status_bit_index  = 0U;
rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

rmIrqReq.src_index              = 30;
rmIrqReq.dst_host_irq           = CSLR_R5FSS0_CORE0_INTR_MCU_MCU_GPIOMUX_INTROUTER0_OUTP_2;

retVal = Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SystemP_WAIT_FOREVER);

src_id is for for MCU GPIO.

src_index=30 value is for MCU_GPIOMUX_INTRTR0 MCU_GPIO_INTRTR_IN_30, which is connected to MCU_GPIO_BANK0_INT.

CSLR_R5FSS0_CORE0_INTR_MCU_MCU_GPIOMUX_INTROUTER0_OUTP_2 (106) is the R5FSS VIM input number corresponding to MCU_GPIOMUX_INTRTR0 Output #2. This is the IRQ number that should be used for interrupt registration (HwiP API) on the R5F.

Regards,
Frank

Hi Tuan,

Please see the AM64x/AM243x TRM, Figure 9-18. MCU_GPIOMUX_INTRTR0 Integration:

• MCU_GPIOMUX_INTRTR0 has 12 Outputs, MCU_MCU_GPIOMUX_INTROUTER0_OUTP_[11:0]
• MCU_MCU_GPIOMUX_INTROUTER0_OUTP_[3:0] are connected to:
  • R5FSS0_CORE0/1 R5FSS0_CORE0/1_INTR_IN_[107:104]
  • R5FSS1_CORE0/1 R5FSS1_CORE0/1_INTR_IN_[107:104]
  • GICSS0 GICSS0_SPI_IN_[107:104]
• Focusing on R5FSS0_CORE0/1, this means:
  • MCU_MCU_GPIOMUX_INTROUTER0_OUTP_0 -> R5FSS0_CORE0/1_INTR_IN_104 (Output #0 is connected to VIM input #104)
  • MCU_MCU_GPIOMUX_INTROUTER0_OUTP_1 -> R5FSS0_CORE0/1_INTR_IN_105 (Output #1 is connected to VIM input #105)
  • MCU_MCU_GPIOMUX_INTROUTER0_OUTP_2 -> R5FSS0_CORE0/1_INTR_IN_106 (Output #2 is connected to VIM input #106)
  • MCU_MCU_GPIOMUX_INTROUTER0_OUTP_3 -> R5FSS0_CORE0/1_INTR_IN_107 (Output #3 is connected to VIM input #107)

Also please see Table 9-81. R5FSS0_CORE1 Interrupt Map, Input Interrupt Line R5FSS0_CORE1_INTR_IN_104 - R5FSS0_CORE1_INTR_IN_107.

Regards,
Frank

Hi Tuan,

This is the hardware route:

• MCU_GPIO0_10 → MCU_GPIO_BANK0_INT
• MCU_GPIO_BANK0_INT → MCU_GPIOMUX_INTRTR0 MCU_GPIO_INTRTR_IN_30
• MCU_GPIOMUX_INTRTR0 MCU_MCU_GPIOMUX_INTROUTER0_OUTP_2 → R5FSS0_CORE0/1 R5FSS0_CORE0/1_INTR_IN_106

MCU_GPIOMUX_INTRTR0 MCU_MCU_GPIOMUX_INTROUTER0_OUTP_2 (Output #2) is configured to select Input #30 (MCU_GPIO_BANK0_INT).

The GPIO interrupt example can be modified for this route and GPIO instance. The example is documented here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/EXAMPLES_DRIVERS_GPIO_INPUT_INTERRUPT.html

I've outlined the required changes below.

Regards,
Frank

Update Resource Management Board Configuration, Assign MCU_GPIOMUX_INTRTR0 Outputs to R5FSS0_CORE0/1

See these docs: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/RESOURCE_ALLOCATION_GUIDE.html

Update <SDK>/source\drivers\sciclient\sciclient_default_boardcfg\am64x_am243x\sciclient_defaultBoardcfg_rm.c as described above: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1087147/processor-sdk-am64x-gpio-interrupt-config-in-am64x-mcu-sdk-08-01-00/4025215#4025215

Rebuild Resource Management Board Configuration as described here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/08_01_00_36/exports/docs/api_guide_am64x/TOOLS_SYSFW.html#BOARCFG_GEN

There is a mistake in the docs concerning building the SBL. For example, if you're using SBL NULL, don't follow the build instructions in the docs. Instead, rebuild the SBL NULL like this: gmake -s -C examples/drivers/boot/sbl_null/am64x-evm/r5fss0-0_nortos/ti-arm-clang

If you're using CCS scripting for SOC initialization instead of the SBL:

• Don't build the SBL. Instead build the sciclient_set_boardcfg application: gmake -s -C examples/drivers/sciclient/sciclient_set_boardcfg/am64x-evm/r5fss0-0_nortos/ti-arm-clang
• Copy generated .out file for sciclient_set_boardcfg application to location where it will be taken by load_dmsc.js:
  • From: <SDK>/examples/drivers/sciclient/sciclient_set_boardcfg/am64x-evm/r5fss0-0_nortos/ti-arm-clang/sciclient_set_boardcfg.release.out
  • To: <SDK>/tools/ccs_load/am64x_am243x/sciclient_set_boardcfg.release.out

Update GPIO Example Application

Update Sysconfig:

• Open example.syscfg, click on GPIO
• Click on "Use MCU Domain Peripherals"
• For GPIO pin, select E7

Update example application:

• Update board.c:Sciclient_gpioIrqSet() as described above: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1087147/processor-sdk-am64x-gpio-interrupt-config-in-am64x-mcu-sdk-08-01-00/4025215#4025215
• Make corresponding changes to board.c:Sciclient_gpioIrqRelease()
• Update board.c, BOARD_BUTTON_GPIO_INTR_NUM:
  #define BOARD_BUTTON_GPIO_INTR_NUM      (CSLR_R5FSS0_CORE0_INTR_MCU_MCU_GPIOMUX_INTROUTER0_OUTP_2)