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DRA821U: DRA821U: MCAN send pending, no MCAN_INTR_SRC_TRANS_COMPLETE received(RTOS+QNX)-Modifications

Part Number: DRA821U

Hi Karan,

Post it here, since can't post on the original thread been resolved.

It's a fifo mismatch like below: 

/*jqsun: rx by fifo*/
if (MCAN_IR_RF0N_MASK == (intrStatus & MCAN_IR_RF0N_MASK)) {
g_fifo_num = 0;
canl_osalPostLock(hdl->rxcomplete);
trace_me("l:ISR0,rxcomplete posted,fifo(0)\n");
}
if (MCAN_IR_RF1N_MASK == (intrStatus & MCAN_IR_RF1N_MASK)) {
g_fifo_num = 1;
canl_osalPostLock(hdl->rxcomplete);
trace_me("l:ISR0,rxcomplete posted,fifo(1)\n");
}

cancsl_readMsgRam(cslhdl,
/*jqsun: fifo or buf??*/
/*MCAN_MEM_TYPE_BUF*/MCAN_MEM_TYPE_FIFO,
0U,
g_fifo_num,
rxmsg);
trace_me("l:can_receive success, payload Bytes:%d\n",
gMcanAppdataSize[rxmsg->dlc]);

switch (fifoNum) {
case MCAN_RX_FIFO_NUM_0:
trace_me("c:cancsl_readMsgRam fifo0\n");
startAddr = HW_RD_FIELD32(hdl->vaddrs.cfg.base + MCAN_RXF0C,
MCAN_RXF0C_F0SA);
elemSize = HW_RD_FIELD32(hdl->vaddrs.cfg.base + MCAN_RXESC,
MCAN_RXESC_F0DS);
idx = HW_RD_FIELD32(hdl->vaddrs.cfg.base + MCAN_RXF0S,
MCAN_RXF0S_F0GI);
enableMod = 1U;
break;
case MCAN_RX_FIFO_NUM_1:
trace_me("c:cancsl_readMsgRam fifo1\n");
startAddr = HW_RD_FIELD32(hdl->vaddrs.cfg.base + MCAN_RXF1C,
MCAN_RXF1C_F1SA);
elemSize = HW_RD_FIELD32(hdl->vaddrs.cfg.base + MCAN_RXESC,
MCAN_RXESC_F1DS);
idx = HW_RD_FIELD32(hdl->vaddrs.cfg.base + MCAN_RXF1S,
MCAN_RXF1S_F1GI);
enableMod = 1U;
break;
default:
/* Invalid option */
break;
}

Regards,

Jianqiang