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Original question:

DRA821U: Is it possible to communicate between two of DRA821s with SGMII I/F without using PHY + MDIO ?

DRA821U: Voltage is applied to SGMII port on DRA821U which is not yet powered

Hideaki Matsumoto
Expert 7695 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821,

Hi,

This is the related question to the following thread, the customer is considering backplane connections via SGMII directly without PHY.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1086351/dra821u-is-it-possible-to-communicate-between-two-of-dra821s-with-sgmii-i-f-without-using-phy-mdio/4026900#4026900

In this case, they have a concern below.

When the module based on DRA821U which is not yet powered inserts into the backplane, then the some signals put into SGMII port on DRA821 earlier than power via PMIC. It means that the voltage is applied to the SGMII port on DRA821 which not yet powered for a little short time.

Is there any problem on this use case ? Does the SGMII port have a tolerance ? Can DRA821 device and software work fine from booting up ?

 

Regards,

Hideaki

  • +1
    TI__Guru 56100 points

    Hideaki-san,

    I referred to the unused pin connections and the abs max rating section on the datasheet.

    Based on that, it is my opinion that the SERDES pins will likely be damaged if they see signals before the power is up and must be avoided.