Hello, TI Experts,
I want to store a 64-bit PCIe memory space in BAR0,1 with PCIe Endpoint.
Start Address:0x00000004_00000000
End Address:0x00000004_00800000
I checked the Technical Reference Manual and set the register, but it didn't work because there wasn't much information about 64-bit.
(Especially for PCIECTRL_EP_DBICS_BAR1 and PCIECTRL_PL_IATU_REG_LIMIT, I didn't know the setting at 64-bit. )
PCIECTRL_EP_DBICS_BAR0(0x51000010)
->0x00000004
PCIECTRL_EP_DBICS_BAR1(0x51000014)
->0x00000004
PCIECTRL_EP_DBICS2_BAR0_BAK(0x51001010)
->0xFFFFFFFF
PCIECTRL_EP_DBICS2_BAR1_BAK(0x51001014)
->0x00000003
PCIECTRL_PL_IATU_REG_LOWER_BASE(0x5100090C)
->0x00000000
PCIECTRL_PL_IATU_REG_UPPER_BASE(0x51000910)
->0x00000004
PCIECTRL_PL_IATU_REG_LIMIT(0x51000914)
->0x00800000
QUESTION:
-Please tell me the register settings that can access the 64-bit memory space.
Best regards,
