I am new on SITARA SoC and I am working on a high throughput system.
I have a question about behavior when several controllers (ARM A15, ARM M4 and DMA) request access at the same time to different devices (McSPI1, McSP2 and McSPI3).
Is the behavior predictable?
Which kind of arbiter is used to grant access to the buses?
Are the buses implemented as shared bus or as cross-bared bus?
Thank you in advance for your help