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AM3359: AM3359

Part Number: AM3359

Hii TI team,

I am working on the Sitara processor(AM3359), and I am using JTAG (BlackHawk 560V2 system trace simulator) . I am getting the following issue -

I am not getting any target configuration.

I can detect JTAG has been connected but for target configuration, I am not able to solve it. 

I am getting the following error:

          The device is held in reset. Take the device out of Reset . The emulation package is 9.5.0.00143

Request to solve the problem.

Thanks and regards,

  • Hello,

              The device is held in reset. Take the device out of Reset . The emulation package is 9.5.0.00143

    Which core are you trying to connect to?

    Thanks

    ki

  • Which core are you trying to connect to?

    I suspect you are trying to connect to the M3 instead of the A8. Most customers are working with the A8 and do not need to connect to the M3. 

    Are you looking to specifically connect to the M3 instead of the A8?

  • I am using Arm cortex A8 (AM3359) Sitara processor.

    when I am using Cortex A, I am getting warning as recommended tool chain for the selected device is GNU. but no build tools are currently installed for this build tool.

    and when I am using Cortex M, I am not getting any recommendations.

    Request to explain this.

    Thanks and regards,

    Jyoti

  • when I am using Cortex A, I am getting warning as recommended tool chain for the selected device is GNU. but no build tools are currently installed for this build tool.

    You must be using CCS 11.x, which does not ship with GCC.

    You can obtain it from App Center:

      :

    Thanks

    ki

  • Test_JTAG[1883].txt
    [Start: Blackhawk XDS560v2-USB System Trace Emulator_0]
    
    Execute the command:
    
    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
    
    [Result]
    
    
    -----[Print the board config pathname(s)]------------------------------------
    
    /home/astra/.ti/ccs1110/0/0/BrdDat/testBoard.dat
    
    -----[Print the reset-command software log-file]-----------------------------
    
    This utility has selected a 560/2xx-class product.
    This utility will load the program 'libbh560v2u.out'.
    Loaded FPGA Image: /home/astra/ti/ccs1110/ccs/ccs_base/common/uscif/./dtc_top.jbc
    The library build date was 'Dec  8 2021'.
    The library build time was '15:33:44'.
    The library package version is '9.6.0.00172'.
    The library component version is '35.35.0.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '6' (0x00000006).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.
    
    -----[Print the reset-command hardware log-file]-----------------------------
    
    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use falling-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: /home/astra/ti/ccs1110/ccs/ccs_base/common/uscif/./dtc_top.jbc
    
    -----[The log-file for the JTAG TCLK output generated from the PLL]----------
    
      Test  Size   Coord      MHz    Flag  Result       Description
      ~~~~  ~~~~  ~~~~~~~  ~~~~~~~~  ~~~~  ~~~~~~~~~~~  ~~~~~~~~~~~~~~~~~~~
        1   none  - 01 00  500.0kHz   -    similar      isit internal clock
        2   none  - 01 09  570.3kHz   -    similar      isit internal clock
        3     64  - 01 00  500.0kHz   O    good value   measure path length
        4     16  - 01 00  500.0kHz   O    good value   auto step initial
        5     16  - 01 0D  601.6kHz   O    good value   auto step delta
        6     16  - 01 1C  718.8kHz   O    good value   auto step delta
        7     16  - 01 2E  859.4kHz   O    good value   auto step delta
        8     16  + 00 02  1.031MHz   O    good value   auto step delta
        9     16  + 00 0F  1.234MHz   O    good value   auto step delta
       10     16  + 00 1F  1.484MHz   O    good value   auto step delta
       11     16  + 00 32  1.781MHz   O    good value   auto step delta
       12     16  + 01 04  2.125MHz   O    good value   auto step delta
       13     16  + 01 11  2.531MHz   O    good value   auto step delta
       14     16  + 01 21  3.031MHz   O    good value   auto step delta
       15     16  + 01 34  3.625MHz   O    good value   auto step delta
       16     16  + 02 05  4.312MHz   O    good value   auto step delta
       17     16  + 02 13  5.188MHz   O    good value   auto step delta
       18     16  + 02 23  6.188MHz   O    good value   auto step delta
       19     16  + 02 37  7.438MHz   O    good value   auto step delta
       20     16  + 03 07  8.875MHz   O    good value   auto step delta
       21     16  + 03 15  10.62MHz   O    good value   auto step delta
       22     16  + 03 1E  11.75MHz  {O}   good value   auto step delta
       23     64  + 02 3E  7.875MHz   O    good value   auto power initial
       24     64  + 03 0E  9.750MHz   O    good value   auto power delta
       25     64  + 03 16  10.75MHz   O    good value   auto power delta
       26     64  + 03 1A  11.25MHz   O    good value   auto power delta
       27     64  + 03 1C  11.50MHz   O    good value   auto power delta
       28     64  + 03 1D  11.62MHz   O    good value   auto power delta
       29     64  + 03 1D  11.62MHz   O    good value   auto power delta
       30     64  + 03 13  10.38MHz  {O}   good value   auto margin initial
    
    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499110Hz.
    The delta frequency was 890Hz.
    
    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569976Hz.
    The delta frequency was 336Hz.
    
    In the scan-path tests:
    The test length was 2048 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.
    
    The IR/DR scan-path tests used 30 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 11.75MHz as the highest frequency.
    The IR/DR scan-path tests used 10.38MHz as the final frequency.
    
    -----[Measure the source and frequency of the final JTAG TCLKR input]--------
    
    The frequency of the JTAG TCLKR input is measured as 10.37MHz.
    
    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.
    
    -----[Perform the standard path-length test on the JTAG IR and DR]-----------
    
    This path-length test uses blocks of 64 32-bit words.
    
    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.
    
    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.
    
    -----[Perform the Integrity scan-test on the JTAG IR]------------------------
    
    This test will use blocks of 64 32-bit words.
    This test will be applied just once.
    
    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.
    
    The JTAG IR Integrity scan-test has succeeded.
    
    -----[Perform the Integrity scan-test on the JTAG DR]------------------------
    
    This test will use blocks of 64 32-bit words.
    This test will be applied just once.
    
    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.
    
    The JTAG DR Integrity scan-test has succeeded.
    
    [End: Blackhawk XDS560v2-USB System Trace Emulator_0]
    
    Hi Ki,

    thanks for reply , i had installed the ARM GCC as suggested still the black hawk usb560V2 system trace is not entering in to the board

    please find the attached error report of in CCS studio 

    test connection in ccs studio -  ccs 11.1.0

    [Start: Blackhawk XDS560v2-USB System Trace Emulator_0]

    Execute the command:

    %ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

    [Result]


    -----[Print the board config pathname(s)]------------------------------------

    /home/astra/.ti/ccs1110/0/0/BrdDat/testBoard.dat

    -----[Print the reset-command software log-file]-----------------------------

    This utility has selected a 560/2xx-class product.
    This utility will load the program 'libbh560v2u.out'.
    Loaded FPGA Image: /home/astra/ti/ccs1110/ccs/ccs_base/common/uscif/./dtc_top.jbc
    The library build date was 'Dec 8 2021'.
    The library build time was '15:33:44'.
    The library package version is '9.6.0.00172'.
    The library component version is '35.35.0.0'.
    The controller does not use a programmable FPGA.
    The controller has a version number of '6' (0x00000006).
    The controller has an insertion length of '0' (0x00000000).
    The cable+pod has a version number of '8' (0x00000008).
    The cable+pod has a capability number of '7423' (0x00001cff).
    This utility will attempt to reset the controller.
    This utility has successfully reset the controller.

    -----[Print the reset-command hardware log-file]-----------------------------

    The scan-path will be reset by toggling the JTAG TRST signal.
    The controller is the Nano-TBC VHDL.
    The link is a 560-class second-generation-560 cable.
    The software is configured for Nano-TBC VHDL features.
    The controller will be software reset via its registers.
    The controller has a logic ONE on its EMU[0] input pin.
    The controller has a logic ONE on its EMU[1] input pin.
    The controller will use falling-edge timing on output pins.
    The controller cannot control the timing on input pins.
    The scan-path link-delay has been set to exactly '2' (0x0002).
    The utility logic has not previously detected a power-loss.
    The utility logic is not currently detecting a power-loss.
    Loaded FPGA Image: /home/astra/ti/ccs1110/ccs/ccs_base/common/uscif/./dtc_top.jbc

    -----[The log-file for the JTAG TCLK output generated from the PLL]----------

    Test Size Coord MHz Flag Result Description
    ~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
    1 none - 01 00 500.0kHz - similar isit internal clock
    2 none - 01 09 570.3kHz - similar isit internal clock
    3 64 - 01 00 500.0kHz O good value measure path length
    4 16 - 01 00 500.0kHz O good value auto step initial
    5 16 - 01 0D 601.6kHz O good value auto step delta
    6 16 - 01 1C 718.8kHz O good value auto step delta
    7 16 - 01 2E 859.4kHz O good value auto step delta
    8 16 + 00 02 1.031MHz O good value auto step delta
    9 16 + 00 0F 1.234MHz O good value auto step delta
    10 16 + 00 1F 1.484MHz O good value auto step delta
    11 16 + 00 32 1.781MHz O good value auto step delta
    12 16 + 01 04 2.125MHz O good value auto step delta
    13 16 + 01 11 2.531MHz O good value auto step delta
    14 16 + 01 21 3.031MHz O good value auto step delta
    15 16 + 01 34 3.625MHz O good value auto step delta
    16 16 + 02 05 4.312MHz O good value auto step delta
    17 16 + 02 13 5.188MHz O good value auto step delta
    18 16 + 02 23 6.188MHz O good value auto step delta
    19 16 + 02 37 7.438MHz O good value auto step delta
    20 16 + 03 07 8.875MHz O good value auto step delta
    21 16 + 03 15 10.62MHz O good value auto step delta
    22 16 + 03 1E 11.75MHz {O} good value auto step delta
    23 64 + 02 3E 7.875MHz O good value auto power initial
    24 64 + 03 0E 9.750MHz O good value auto power delta
    25 64 + 03 16 10.75MHz O good value auto power delta
    26 64 + 03 1A 11.25MHz O good value auto power delta
    27 64 + 03 1C 11.50MHz O good value auto power delta
    28 64 + 03 1D 11.62MHz O good value auto power delta
    29 64 + 03 1D 11.62MHz O good value auto power delta
    30 64 + 03 13 10.38MHz {O} good value auto margin initial

    The first internal/external clock test resuts are:
    The expect frequency was 500000Hz.
    The actual frequency was 499110Hz.
    The delta frequency was 890Hz.

    The second internal/external clock test resuts are:
    The expect frequency was 570312Hz.
    The actual frequency was 569976Hz.
    The delta frequency was 336Hz.

    In the scan-path tests:
    The test length was 2048 bits.
    The JTAG IR length was 6 bits.
    The JTAG DR length was 1 bits.

    The IR/DR scan-path tests used 30 frequencies.
    The IR/DR scan-path tests used 500.0kHz as the initial frequency.
    The IR/DR scan-path tests used 11.75MHz as the highest frequency.
    The IR/DR scan-path tests used 10.38MHz as the final frequency.

    -----[Measure the source and frequency of the final JTAG TCLKR input]--------

    The frequency of the JTAG TCLKR input is measured as 10.37MHz.

    The frequency of the JTAG TCLKR input and TCLKO output signals are similar.
    The target system likely uses the TCLKO output from the emulator PLL.

    -----[Perform the standard path-length test on the JTAG IR and DR]-----------

    This path-length test uses blocks of 64 32-bit words.

    The test for the JTAG IR instruction path-length succeeded.
    The JTAG IR instruction path-length is 6 bits.

    The test for the JTAG DR bypass path-length succeeded.
    The JTAG DR bypass path-length is 1 bits.

    -----[Perform the Integrity scan-test on the JTAG IR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG IR Integrity scan-test has succeeded.

    -----[Perform the Integrity scan-test on the JTAG DR]------------------------

    This test will use blocks of 64 32-bit words.
    This test will be applied just once.

    Do a test using 0xFFFFFFFF.
    Scan tests: 1, skipped: 0, failed: 0
    Do a test using 0x00000000.
    Scan tests: 2, skipped: 0, failed: 0
    Do a test using 0xFE03E0E2.
    Scan tests: 3, skipped: 0, failed: 0
    Do a test using 0x01FC1F1D.
    Scan tests: 4, skipped: 0, failed: 0
    Do a test using 0x5533CCAA.
    Scan tests: 5, skipped: 0, failed: 0
    Do a test using 0xAACC3355.
    Scan tests: 6, skipped: 0, failed: 0
    All of the values were scanned correctly.

    The JTAG DR Integrity scan-test has succeeded.

    [End: Blackhawk XDS560v2-USB System Trace Emulator_0]

    request to help us to release this black hawk usb560v2 from rest as shown in the above figure 

    regards

    jyoti

  • Your low level JTAG connectivity is good. The error you are seeing is higher level and has many potential root causes. 

    Please see the below link for more details on the error:

    https://software-dl.ti.com/ccs/esd/documents/ccs_debugging_jtag_connectivity_issues.html#cannot-access-the-dap

    Also, are you using an EVM or is this a custom board?

    Thanks

    ki

  • custom board

    regards

    jyoti

  • Have you ever connected to this board before?

    Did you run the install_drivers.sh as sudo after CCS installation?

  • yes we had connected before and working , only difference is new usb560v2 system tracer ,because earlier devices had some usb connective , with this the script files are not available in ccs studio and GEL file is not available , can you help in finding the GEL file of AM335x.gel , we are not able to find the initialization script file  of Cortex A8 core 

    regards

    jyoti

  • we had also run the install_drivers.sh also after instillation

  • can you help in finding the GEL file of AM335x.gel

    I'm not sure where that file is from. I don't see it on my system. 

    The closest gel files I can find are the ones in:

    <CCS INSTALL DIR>\ccs\ccs_base\emulation\boards\evmam3358\gel

    <STARTERWARE INSTALL DIR>\tools\gel