Hello experts
With a custom board we are running into an issue with PCIe
(despite not being the first board where we put it in use with this processor)
the setup :
- one 66AK2H14 as root complex running Linux
- a PCIe switch component
- several 66AK2H14 as endpoints running TI-RTOS
- one FPGA
the Root Complex does its PCIe enumeration and detects all endpoints
Memory Read Write from the Root complex to the FPGA --> works
BUT
memory write from one AK2H14 Endpoint to the FPGA --> no errors reported
memory READ from one AK2H14 Endpoint to the FPGA --> errors reported
The AK2h14 Endpoint reports a received master abort error
(RX_MST_ABORT bit set in STATUS_COMMAND register, which means it received "a completion with unsupported request completion status"
The PCIe switch port connected to the AK2H14 endpoint sees :
Correctable Error Detected and Unsupported Request Detected on DEVICE STATUS register
Advisory Non-Fatal Error status on CORRECTABLE ERROR STATUS register
we have checked the obvious (bus master enable etc.) but doesn't see why the transaction is rejected ?
--> any ideas?
Thanks
