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PROCESSOR-SDK-AM64X: AM64x CCS debugger problem



I've written some test code for doing DDR DMA transfers, based on the udma_memcpy_interrupt.c code. The code fills 4K of DDR memory (0x80000000 - 0x80000FFF) with 32 bit data.
I then run the test code to do the DMA transfer. The code reaches the interrupt handler successfully. However, when I look at the destination buffer (starting at 0x80002000) I only see small sections of data appear.
I've run into similar situations before on Eclipse based debuggers, where the memory window doesn't get updated (I did try doing a memory refresh with no success). If I kill the debug session and restart it, most of the data does appear in the destination buffer. In this case, I also see sections of the source buffer have disappeared. The missing source data is mirrored in the destination buffer.

It appears that the DMA code works, but I'm having difficulty telling whether the problem is in the DMA code or the debugger (possibly somewhere else?) Any suggestions would be appreciated.

Lee Thalblum

  • Hi,

    that sounds a lot like caching effects. Are the sections that you see possibly 32 byte aligned? That's the R5 (I'm guessing you're using the R5?) cache line size. 

    Did you make sure caches for this region are either disabled or were invalidated before you started the DMA?

    Regards, Dominic

  • Hi Lee,

    This looks like a cache alignment issue.
    Please make sure that buffers are either aligned to cache line size or are located in a non-cacheable region.

    To align buffers to cache size you can do something like this:-
    uint32_t gAdcDestBuf[UDMA_ALIGN_SIZE(BUFFER_SIZE)] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));

    After receiving a DMA completion interrupt make sure to perform a cache invalidate operation before consuming the buffer

     CacheP_inv(&gAdcDestBuf[0U], sizeof(gAdcDestBuf), CacheP_TYPE_ALLD);

    For more information on cache maintenance refer to :-

    For creating a non cacheable region you need to setup MPU region and disable cacheability for that address.


  • Hi Rajat,

    This does appear to be a cache alignment issue. I disabled caching for the DDR region in sysCfg and the problem no longer appears. Thanks for your help.

    I read a number of references on caching and still have some questions.

    In the final design, some regions of DDR will be shared between the AM64x A core and a single R core. These regions will use DMA to transmit and receive data from a peripheral on the R core. Are there any drawbacks or issues that need to be taken into account in this case?
    Can I just disable caching in these regions? 


  • Hi Lee,

    It depends on how the data is consumed.

    This is very application dependent and the only way to be sure is to benchmark both approaches (with cache maintenance and with region as non-cacheable) and make a decision.

    Just a note that the mpu settings that you do for R5 are only applicable to that R5.


  • Thanks again Rajat. I'll have to run tests when I get to that part of the project.