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Original question:

PROCESSOR-SDK-AM64X: icssg wrong content of received frames

PROCESSOR-SDK-AM64X: activate cache in FreeRTOS Linker script

Daniel Schmid
Prodigy 150 points
Part Number: PROCESSOR-SDK-AM64X
Other Parts Discussed in Thread: SYSCONFIG

Hi folks!

In my application a had performance problems.

I started with the this example linker script

mcu_plus_sdk_am64x_08_01_00_36\examples\networking\lwip\enet_lwip_cpsw\am64x-evm\r5fss0-0_freertos\ti-arm-clang\linker.cmd

here every think is slow.

So I moved the code block 

.text:   {} palign(8)   /* This is where code resides */

from the 

GROUP { .. } > DDR

to 

GROUP { .. } > MSRAM

Now every thing is much faster,

but does this mean the code isn't cached?

How can I activate caching?

Best Regards

Daniel

  • 0
    TI__Intellectual 1155 points

    Hi,

    The caching on ARM cores requires two configurations to be done.

    1- Enabling the cache itself
    2- Setting up Memory protection unit to configure a specific area to be cacheable or not (by default set to cacheable)

    If you are starting from the empty example project in MCU+ SDK the caches are enabled. You can use MPU settings in sysconfig to define a region that you wish to be non-cacheable.

    You can look at the linker region you are placing the data in and then check MPU configuration to be sure if MPU configures that region as cacheable or not.

     Let me know if you need further clarification.

    Regards