Hi,
Customer communicates with the FPGA through SRIO (refer to the routine ti\pdk_c667x_2_0_16\packages\ti\drv\srio\example\SRIOLoopbackDioIsr), and configure it in 4x mode, only when the values of SWAP_RX and SWAP_TX are both set to 2 (PLM Port(n) Implementation Specific Control Register) SrioDevice_init() can return successfully. Otherwise it will be stuck in while (CSL_SRIO_IsPortOk (hSrio, 0) != TRUE);
How to determine if there is a problem with the lane sequence in SRIO 4x mode?
Hi Nancy,
configure it in 4x mode, only when the values of SWAP_RX and SWAP_TX are both set to 2 (PLM Port(n) Implementation Specific Control Register)
As mentioned in below picture, for 4x lane needs to be set up at value "2" (b010)
on page 280 of https://www.ti.com/lit/ug/sprugw1c/sprugw1c.pdf and to get lane status
How to determine if there is a problem with the lane sequence in SRIO 4x mode?
use "CSL_SRIO_GetLaneStatus()" API function from the CSL library can be used and tie them to an event.
Thanks
Rajarajan U
