DRA829J: CPSW9G serdes4_0 clk src register could not write , program stuck at sgmii link state check

Part Number: DRA829J

Hi,

I tried to debug mac to mac on SGMII port 5 & port 8.

I configured the SGMII mode to ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK.

And I found SGMII port5 always stay at 'get SGMII status' as below:

There is no error information output in UART. And the value of register '0C000514h' is 0x00000030.

The SGMII port8 is the same as port5 and always stay at 'get SGMII status', but the value of register '0C000814h' is 0x0000003a. 

I found the PLL of port8 sometime can't be locked,  and sometimes can be locked.

 

Above all, the SGMII5 & 8 cann't link up. Do you have any suggestions to handle this issue? Thank you!

And for above if there is anything wrong, please tell us and I will try to debug it.

 

Best regards,

Lan

  • Lan, 

    can you confirm which register did you check when you noticed "PLL of port8 sometimes can't be locked"? I assume you already checked other registers alone the signal path:

    1. SERDES4 PLL lock status register

    2. SERDES4 Lane 3 LANESTS3, LANECTL3 registers

    3. CTRLMMR_ENET8_CTRL and CTRLMMR_SERDES4_LN3_CTRL

    4. CPSW9G SGMII Control and Status registers. In Control register, enable Master mode. 

    Let me know any of these notes helps.

    JIan

  • Hi Jian, 

    Thank you for your reply, and we really need your help.

    I got the register value as bellow:

    1. CPSW_SGMII_STATUS_REG_j Register(0x0C000814)=> 0x00000038
    It dicated that PLL is locked, correct?

    2. SERDES4 Lane 3 LANESTS3(0x0505054Ch) ==> 0x00000002
    LANECTL3 registers(0x05050540) ==> 0x00000000

    3. CTRLMMR_ENET8_CTRL(0x00104060) ==》0x00000003
    CTRLMMR_SERDES4_LN3_CTRL(0x001040CC) ==》0x00000002

    4. CPSW9G SGMII Control (0x0C000814) => 0x00000038
    CPSW9G tatus register(0x0C000810) => 0x00000020

    Is there anything wrong for the above information? And the SGMII can not link up. How can I debug or modify some configuration? Please 

    give me some guidence. Thanks a lot.

    Best regards,

    Lan

  • Hi,

    In addition to ethfw, we also test the loopback demo.

    When we set loopback level to mac loopback, the test result is PASS,  as following:

    But when we set loopback level to PHY loopback, the SGMII can't link up. The register status is following:

    We can see that the SerDes PLL is locked, and the SGMII Advertised Ability is correct. But the SGMII Link Partner Advertised Ability is wrong.

    At the PHY side, we have set the advertised ablitily to 1Gbps/Full Duplex. And now SGMII5/6 can't link up. We want to know how to debug and

    handle this issue(SGMII 5/6 can't link up). Please help us and give us some debug suggestion, Thanks a lot.

    Best Regards,

    Lan