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TDA4VM: TDA4VM-Q1: can_boot_app_mcu_rtos (CAN FAST Response) didn't work on SDK8.2

june lee
Prodigy 220 points
Part Number: TDA4VM

Hello TI Teams:

I am building the can_boot_app_mcu_rtos , it's didn't work on my side. i hadn't modify the makefiles,  and i tried to set CANFUNC ?= none , but it still has the same error. Please help to check . Thanks.

 $ make -s -j can_boot_app_mcu_rtos BOARD=j721e_evm SOC=j721e BUILD_PROFILE=release CORE=mcu1_0 BUILD_OS_TYPE=freertos            
Nothing to be done for j721e i2c_profile
Nothing to be done for j721e i2c_indp
Nothing to be done for j721e i2c_icss0
Nothing to be done for j721e i2c_profile_indp
# Check and update: src/version/rmpmhal_version.h
Nothing to be done for j721e fatfs_multi_indp
fatal: 没有附注标签能描述 '7a5bc0fed9f28f3a929f3a641835b1558819fa97'。
然而，存在未附注标签：尝试 --tags。
# Check and update: src/version/sciserver_version.h
fatal: 没有附注标签能描述 '7a5bc0fed9f28f3a929f3a641835b1558819fa97'。
然而，存在未附注标签：尝试 --tags。
Building MCUSW CAN Boot App with BISTFUNC=disabled, BOOTFUNC=enabled, HLOSBOOT=none, BOOTMODE=ospi, CANFUNC=can_fast_response, DEVICETYPE=GP, BUILD_OS_TYPE=freertos, ENABLE_OSPI_DMA=no and MCUONLYFUNC=disabled
Building MCUSW CAN Boot App with BISTFUNC=disabled, BOOTFUNC=enabled, HLOSBOOT=none, BOOTMODE=ospi, CANFUNC=can_fast_response, DEVICETYPE=GP, BUILD_OS_TYPE=freertos, ENABLE_OSPI_DMA=no and MCUONLYFUNC=disabled
# Compiling j721e_evm:j721e:mcu1_0:release:app_utils:src/app_utils.c
# Compiling j721e_evm:j721e:mcu1_0:release:app_utils:src/app_r5f_Pmu.c
# Compiling j721e:mcu1_0:release:can:src/Can.c
# Compiling j721e:mcu1_0:release:can:src/Can_Priv.c
# Compiling j721e:mcu1_0:release:can:src/Can_Irq.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Det/src/Det.c
# Compiling j721e:mcu1_0:release:dio:src/Dio.c
# Compiling j721e_evm:j721e:mcu1_0:release:demo_utils:src/utils_prf_rtos.c
# Compiling j721e:mcu1_0:release:can:src/Can_Mcan.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Dem/src/Dem.c
# Compiling j721e:mcu1_0:release:dio:src/Dio_PlatformJ721e.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Os/src/Os.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Rte/src/SchM_Spi.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Rte/src/SchM_Can.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Rte/src/SchM_Dio.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Rte/src/SchM_Eth.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Rte/src/SchM_EthTrcv.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Rte/src/SchM_Gpt.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:EcuM/src/EcuM_Cbk.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:Rte/src/SchM_Cdd_Ipc.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:CanIf/src/CanIf.c
# Compiling j721e:mcu1_0:release:bsw_stubs_rtos:CanIf/src/CanIf_Cbk.c
#
# Archiving j721e_evm:j721e:mcu1_0:release:app_utils into /home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/mcal/examples/utils/lib/j721e_evm/mcu1_0/release/app_utils.aer5f ...
#
#
#
# Archiving j721e_evm:j721e:mcu1_0:release:demo_utils into /home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/mcuss_demos/demo_utils/lib/j721e_evm/r5f/release/demo_utils.aer5f ...
# Archiving j721e:mcu1_0:release:dio into /home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/mcal/Dio/lib/j721e/mcu1_0/release/dio.aer5f ...
#
#
#
# Archiving j721e:mcu1_0:release:bsw_stubs_rtos into /home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/mcuss_demos/Bsw_Stubs/lib/j721e/r5f/release/bsw_stubs_rtos.aer5f ...
#
#
# Archiving j721e:mcu1_0:release:can into /home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/mcal/Can/lib/j721e/mcu1_0/release/can.aer5f ...
#
Building MCUSW CAN Boot App with BISTFUNC=disabled, BOOTFUNC=enabled, HLOSBOOT=none, BOOTMODE=ospi, CANFUNC=can_fast_response, DEVICETYPE=GP, BUILD_OS_TYPE=freertos, ENABLE_OSPI_DMA=no and MCUONLYFUNC=disabled
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos: /home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/mcal_drv/mcal/examples/utils/src/utilsCopyVecs2ATcm.asm
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:main_tirtos.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:soc/j721e/boot_core_defs.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:overrides/j721e/mcu1_0/r5_mpu_freertos.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:mcu_timer_multicore.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:can_resp.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:can_utils.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:boot.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/mcuss_demos/mcal_config/Can_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Can_Cfg.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/mcuss_demos/mcal_config/Can_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Can_PBcfg.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/mcuss_demos/mcal_config/Dio_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Dio_Lcfg.c
# Compiling j721e_evm:j721e:mcu1_0:release:can_boot_app_mcu_rtos:/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/mcal_drv/mcal/examples/utils/src/app_utils_can.c
# Linking into /home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/can_boot_app_mcu_rtos/bin/j721e_evm/can_boot_app_mcu_rtos_mcu1_0_release.xer5f...
#
"/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/mcuss_demos/boot_app_mcu_rtos/overrides/j721e/mcu1_0/linker_r5_freertos.lds", line 121: error #10099-D: 
   program will not fit into available memory, or the section contains a call
   site that requires a trampoline that can't be generated for this section.
   placement with alignment fails for section ".cinit" size 0x2b2e.  Available
   memory ranges:
   OCMC_RAM_SCISERVER   size: 0x60000      unused: 0xe36        max hole: 0x7d0
error #10010: errors encountered during linking;
   "/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/can_boot_app_mcu_rtos/bin
   /j721e_evm/can_boot_app_mcu_rtos_mcu1_0_release.xer5f" not built
tiarmclang: error: tiarmlnk command failed with exit code 1 (use -v to see invocation)
/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/pdk_jacinto_08_02_00_21/packages/ti/build/makerules/rules_ti_cgt_arm.mk:349: recipe for target '/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/can_boot_app_mcu_rtos/bin/j721e_evm/can_boot_app_mcu_rtos_mcu1_0_release.xer5f' failed
make[2]: *** [/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/mcusw/binary/can_boot_app_mcu_rtos/bin/j721e_evm/can_boot_app_mcu_rtos_mcu1_0_release.xer5f] Error 1
/home/tda4/SDK_8_2/sdk8_2_qnx/PSDKRA/pdk_jacinto_08_02_00_21/packages/ti/build/makerules/common.mk:410: recipe for target 'mcu1_0' failed
make[1]: *** [mcu1_0] Error 2
makefile:148: recipe for target 'can_boot_app_mcu_rtos' failed
make: *** [can_boot_app_mcu_rtos] Error 2

  • 0
    Prodigy 220 points

    Hello， TI Teams:

    Can you pls help to check and give your comments ? Thanks. 

    Regards, 

  • 0 in reply to june lee
    TI__Mastermind 32377 points

    Hi June,

    We are investigating this issue, I will get back to you with our results.

    Regards,

    Erick

  • 0 in reply to Erick Narvaez
    TI__Guru* 75222 points

    Hi,

    Can you use the below diff and try?

    diff --git a/mcuss_demos/boot_app_mcu_rtos/makefile b/mcuss_demos/boot_app_mcu_rtos/makefile
index 56ed7f4..31d97ad 100755
--- a/mcuss_demos/boot_app_mcu_rtos/makefile
+++ b/mcuss_demos/boot_app_mcu_rtos/makefile
@@ -1,10 +1,10 @@
 # Default bootmode for Main domain cores is via MMCSD, unless specified at command line differently
 #BOOTMODE ?= mmcsd
-BOOTMODE ?= ospi
+BOOTMODE ?= mmcsd
 # Default OSPI DMA to "no" (disabled).  Change to "yes", if building PDK SBL with -DSBL_USE_DMA=1
 ENABLE_OSPI_DMA ?= no
 # CAN Boot Function options are can_profiling, can_fast_response, or none
-CANFUNC ?= can_fast_response
+CANFUNC ?= none
 #CANFUNC ?= can_profiling
 #CANFUNC ?= none
 # Boot function options are enabled or disabled

    In OSPI boot mode, the code size is increasing and hence giving you an error in linking.

    Please note, using the above patch you will need to boot in MMCSD boot mode.

    Regards

    Karan

  • 0 in reply to Karan Saxena
    Prodigy 220 points

    Hi Karan:

         I want to use BOOTMODE = OSPI. So i want to make sure that the code size is indeed increased in SDK8_2 ? and the OCMC_RAM_SCISERVER also increase in SDK8.2.

             

  • 0 in reply to june lee
    TI__Guru* 75222 points

    Hi,

    The size of the code has increased due to migration to the TI CLANG.

    Do you want the functionality to boot other cores?

    Regards

    Karan

  • 0 in reply to Karan Saxena
    Prodigy 220 points

    yes, i wan to use it to boot other cores, then restart MCU1_0/MCU1_1, i modify the code in the boot.c

        /* Delay print out of boot log to avoid prints by other tasks */
	for(j = 0; j < NUM_BOOT_STAGES; j++)
	{
            num_cores_to_boot = num_cores_per_boot_stage[j];
            boot_array        = boot_array_stage[j];
            for (i = 0; i < num_cores_to_boot; i++)
            {
                core_id = boot_array[i];
                /* Try booting all cores other than the cluster running the SBL */
                if ((k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR) &&
                    ((core_id != MCU1_CPU1_ID) && (core_id != MCU1_CPU0_ID)))
                {
                    SBL_SlaveCoreBoot(core_id, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
					TaskP_sleep(40);

                }
				//TaskP_sleep(10);
            }
//TaskP_sleep(10);
	}

	
	    SBL_SlaveCoreBoot(MCU1_CPU0_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);
		SBL_SlaveCoreBoot(MCU1_CPU1_ID, 0, &k3xx_evmEntry, SBL_REQUEST_CORE);

  • 0 in reply to june lee
    TI__Guru* 75222 points

    Hi,

    Can you see if with the default SDK makefile but by updating the linker file to below works?

    From af38e70115843c1503225fb8a4ca1d3618560a66 Mon Sep 17 00:00:00 2001
From: Karan Saxena <karan@ti.com>
Date: Wed, 25 May 2022 18:55:01 +0530
Subject: [PATCH] Update memory map for boot_app_mcu_rtos

Signed-off-by: Karan Saxena <karan@ti.com>
---
 .../j721e/mcu1_0/linker_r5_freertos.lds       | 50 +++++++++----------
 1 file changed, 24 insertions(+), 26 deletions(-)

diff --git a/mcuss_demos/boot_app_mcu_rtos/overrides/j721e/mcu1_0/linker_r5_freertos.lds b/mcuss_demos/boot_app_mcu_rtos/overrides/j721e/mcu1_0/linker_r5_freertos.lds
index fb5a64e..dd1a72d 100755
--- a/mcuss_demos/boot_app_mcu_rtos/overrides/j721e/mcu1_0/linker_r5_freertos.lds
+++ b/mcuss_demos/boot_app_mcu_rtos/overrides/j721e/mcu1_0/linker_r5_freertos.lds
@@ -88,14 +88,12 @@ MEMORY
     /* Used in this file */
     MCU0_DDR_SPACE (RWIX)     : origin=0xA0400000 length=0xC00000       /* 12MB */
 
-    RESERVED (X)            : origin=0x41C3E000 length=0x2000
     /* Refer the user guide for details on persistence of these sections */
+
     OCMC_RAM_BOARD_CFG (RWIX)   : origin=0x41C80000 length=0x2000
-    OCMC_RAM_SCISERVER (RWIX)   : origin=0x41C82000 length=0x60000
-    RESET_VECTORS (X)           : origin=0x41CE2000 length=0x100
-    OCMC_RAM (RWIX)             : origin=0x41CE2100 length=0x1DA00
+    OCMC_RAM (RWIX)             : origin=0x41C82000 length=0x7DA00
     OCMC_RAM_X509_HEADER (RWIX) : origin=0x41CFFB00 length=0x500
-
+    OCMC_RAM_SBL_RUNTIME (RWIX) : origin=0x41C00000 length=0x80000
 
 }  /* end of MEMORY */
 
@@ -108,33 +106,33 @@ SECTIONS
     .bootCode        : {} palign(8)      > OCMC_RAM
     .startupCode     : {} palign(8)      > OCMC_RAM
     .startupData     : {} palign(8)      > OCMC_RAM, type = NOINIT
-    .text    	: {} palign(8) 		> OCMC_RAM_SCISERVER
+    .text    	: {} palign(8) 		> OCMC_RAM
     GROUP {
         .text.hwi    : palign(8)
         .text.cache  : palign(8)
         .text.mpu    : palign(8)
         .text.boot   : palign(8)
-    }                           > OCMC_RAM_SCISERVER
-    .text    	: {} palign(8) 		> OCMC_RAM_SCISERVER
+    }                           > OCMC_RAM
+    .text    	: {} palign(8) 		> OCMC_RAM
     .const   	: {} palign(8) 		> OCMC_RAM
     .rodata   : {} palign(8)    > OCMC_RAM
-    .cinit   	: {} palign(8) 		> OCMC_RAM_SCISERVER
-    .pinit   	: {} palign(8) 		> OCMC_RAM_SCISERVER
+    .cinit   	: {} palign(8) 		> OCMC_RAM
+    .pinit   	: {} palign(8) 		> OCMC_RAM
 
     /* For NDK packet memory, we need to map this sections before .bss*/
     .bss:NDK_MMBUFFER  (NOLOAD) {} ALIGN (128) > MCU0_DDR_SPACE
     .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > MCU0_DDR_SPACE
 
-    .bss     	: {} align(4)  	> OCMC_RAM_SCISERVER
-    .far     	: {} align(4)  	> OCMC_RAM_SCISERVER
-    .data    	: {} palign(128) 	> OCMC_RAM_SCISERVER
-    .data_buffer: {} palign(128) 	> OCMC_RAM_SCISERVER
-	.sysmem  	: {}                > OCMC_RAM_SCISERVER
-	.stack  	: {} align(4)		> OCMC_RAM_SCISERVER  (HIGH) fill=FILL_PATTERN
-    .bss.devgroup* : {} align(4)      > OCMC_RAM_SCISERVER
-    .const.devgroup*: {} align(4)     > OCMC_RAM_SCISERVER
-    .data_user      : {} align(4)      > OCMC_RAM_SCISERVER
-    .boardcfg_data  : {} align(4)      > OCMC_RAM_SCISERVER
+    .bss     	: {} align(4)  	> OCMC_RAM_SBL_RUNTIME
+    .far     	: {} align(4)  	> OCMC_RAM
+    .data    	: {} palign(128) 	> OCMC_RAM
+    .data_buffer: {} palign(128) 	> OCMC_RAM
+	.sysmem  	: {}                > OCMC_RAM
+	.stack  	: {} align(4)		> OCMC_RAM  (HIGH) fill=FILL_PATTERN
+    .bss.devgroup* : {} align(4)      > OCMC_RAM
+    .const.devgroup*: {} align(4)     > OCMC_RAM
+    .data_user      : {} align(4)      > OCMC_RAM
+    .boardcfg_data  : {} align(4)      > OCMC_RAM
 
     /* USB or any other LLD buffer for benchmarking */
     .benchmark_buffer (NOLOAD) {} ALIGN (8) > OCMC_RAM
@@ -144,24 +142,24 @@ SECTIONS
     .sysfw_data_cfg_board_rm   : {} palign(128) > OCMC_RAM
     .sysfw_data_cfg_board_sec  : {} palign(128) > OCMC_RAM
 
-	.stack  	: {} align(4)		> OCMC_RAM_SCISERVER (HIGH)
-    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > OCMC_RAM_SCISERVER  (HIGH)
+	.stack  	: {} align(4)		> OCMC_RAM (HIGH)
+    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > OCMC_RAM  (HIGH)
     RUN_START(__IRQ_STACK_START)
     RUN_END(__IRQ_STACK_END)
 
-    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > OCMC_RAM_SCISERVER  (HIGH)
+    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > OCMC_RAM  (HIGH)
     RUN_START(__FIQ_STACK_START)
     RUN_END(__FIQ_STACK_END)
 
-    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > OCMC_RAM_SCISERVER  (HIGH)
+    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > OCMC_RAM  (HIGH)
     RUN_START(__ABORT_STACK_START)
     RUN_END(__ABORT_STACK_END)
 
-    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > OCMC_RAM_SCISERVER  (HIGH)
+    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > OCMC_RAM  (HIGH)
     RUN_START(__UND_STACK_START)
     RUN_END(__UND_STACK_END)
 
-    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > OCMC_RAM_SCISERVER  (HIGH)
+    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > OCMC_RAM  (HIGH)
     RUN_START(__SVC_STACK_START)
     RUN_END(__SVC_STACK_END)
 
-- 
2.17.1

    0001-Update-memory-map-for-boot_app_mcu_rtos.zip

    Regards

    Karan

  • 0 in reply to Karan Saxena
    Prodigy 220 points

    yes, it works. i want to boot my app(run in the MCU1_0) by can_boot program, Does it mean i couldn't  use the  segment from 0x41c82000 to 0x41c82000+7da00, because it has sci server's codes.

  • +1 in reply to june lee
    TI__Guru* 75222 points

    Hi,

    You can use the rest of the OCM_RAM section. The sciserver code along with your code can be a part of this section.

    Regards

    Karan