Hi,
Customer clear TIMHIRS and TIMLORS, but TSTAT_LO and TSTAT_HI are not reset to 0.
3.6 Timer Reset Sources
https://www.ti.com.cn/cn/lit/ug/sprugv5a/sprugv5a.pdf
TImer mode is dual 32bit unchain mode. Is there a demo available for reference?
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Hi,
Customer clear TIMHIRS and TIMLORS, but TSTAT_LO and TSTAT_HI are not reset to 0.
3.6 Timer Reset Sources
https://www.ti.com.cn/cn/lit/ug/sprugv5a/sprugv5a.pdf
TImer mode is dual 32bit unchain mode. Is there a demo available for reference?
Hi Nancy,
Timer example is available TI-RTOS SDK. I will update the code reference and project examples ASAP.
Thanks,
Rajarajan U
Hi,
Thanks!
Is there a reference code for the customer's problem? Or how to debug?
Hi Nancy,
Is there a reference code for the customer's problem?
Reference code or project is not available for the customer's problem.
But, the CSL APIs have been available for Timer configuration (These APIs abstract the register access, but all the necessary functionality was included).
Location :
"TIRTOS_SDK_FOLDER}/pdk_c667x_2_0_16/packages/ti/csl/docs/doxygen/html/group___c_s_l___t_i_m_e_r___f_u_n_c_t_i_o_n.html" (Kindly open this API documentation in browser).
For example : CSL_TmrReset64(CSL_TmrHandle hTmr) resets the 64-bit timer which in turn sets TMR_TGCR_TIMLORS=0,TMR_TGCR_TIMHIRS=0.
Thanks,
Rajarajan U