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AM5718: Mutual exclusion mechanism between A15 core and DSP core

Part Number: AM5718

Hi,

Customer encountered a problem when using A15 core and DSP core to read and write CMEM at the same time:

1、There is no problem with CMEM reading and writing data

2、In a CMEM space, A15 changes and writes data in a 1ms cycle each time, and DSP reads data in a 1ms cycle, but the read data will be abnormal. For example:

A15 first write {0,1,2,3,4,5,6} and {a,b,c,d,e,f,g} for the second time, the data read by DSP may be {a,b,c,d,4,5,6};

3、The way of writing and reading is memcpy copied directly from CMEM

4、Because the ipc or mailbox delay is too large, the customer does not want to achieve this with IPC or mailbox notification

Is there a mutual exclusion mechanism to avoid this problem?