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AM5728: Support of 8bit BT.656 data out on VOUT2 port of AM5728

Part Number: AM5728


We have configured connected ADV7391 on VOUT2 port of AM5728. We want to display CVBS video on LCD.

Following is the HW pipeline

AM5728 DSS VOUT2(BT656) -> ADV7391(video encoder) -> LCD(CVBS)

We have followed below mentioned document to bypass video pipeline as mentioned in section 2.3.2

https://www.ti.com/lit/an/sprac16a/sprac16a.pdf

we had tried to modify in existing software driver to configure DSS BT656 for 8 bit interface.

Following is the device tree changes:

&dss {
ports {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";

port@1 {
reg = <1>;
dpi_out2: endpoint {
data-lines = <16>;
remote-endpoint = <&adv7391_in>;
};
};
port@2 {
reg = <2>;
dpi_out: endpoint {
data-lines = <24>;
remote-endpoint = <&lcd_in>;
};
};

};
};

sample-panel.c changes:

static const struct panel_desc pdic_display_adv7391 = {
.modes = &pdic_display_adv7391_mode,
.num_modes = 1,
.bpc = 8,
.size = {
.width = 130,
.height = 98,
},
.bus_format = MEDIA_BUS_FMT_RGB565_1X16,
};

The changes of DSS driver Attached

Request your help in below points on software side:

  • Is it possible to run BT.656 mode with external sync?

  • What should be AM5728 configuration for DSS to output YUV422 8-bit (BT.656) with embedded sync and/or external sync?



  • Hi,

    Is it possible to run BT.656 mode with external sync?

    No, BT656 is embedded sync output, in this case, there are not external sync signals.

    What should be AM5728 configuration for DSS to output YUV422 8-bit (BT.656) with embedded sync and/or external sync?

    Can you please refer to below FAQ? This has been validated with ADV7393, not sure if similar mechanism can be used for ADV7391.

    https://www.ti.com/lit/an/sprac23a/sprac23a.pdf?ts=1654248931546&ref_url=https%253A%252F%252Fwww.google.com%252F

    Regards,

    Brijesh

  • Thanks for the response. We have gone through your provided link. All the data mentioned for ADV7393 16-bit interface. In our case, we are using ADV7391 and its 8-bit interface. 

    In our previously attached patch, we have modified for 8-bit but no success.  

    Is there any limitation from technical point of view to support 8-bit output interface as we see one register DISPC_CONTROLx[Bit 9:8], TFTDATALINES has no configuration for 8-bit output aligned interface settings ? However, we have tried to configure RGB888 and RGB565 input for 8-bit output interface.

  • We have followed the link mention in above thread www.ti.com/.../sprac23a.pdf and section 3 reference DSS Bit Exact Output for our development.

    We have modified below changes as per document.

    • As per Section 2.3.1- provided RGB888 input – 8bit output interface with below changes:

      Below is the dump of the register of DSS system.

      All values are in HEX.

      DISPC_CONTROL2 0x01100309

      DISPC_CONFIG2 0x00000000

      DISPC_OVL_ATTRIBUTES(VID2) 0x02808400

      DISPC_DATA_CYCLE1(LCD2) 0x00000008

      DISPC_DATA_CYCLE2(LCD2) 0x00000008

      DISPC_DATA_CYCLE3(LCD2) 0x00000008

      DISPC_CONTROL2 01100309

      DISPC_CONFIG2 00000000

      Below is the snapshot of the lcd timing structure.

      <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

      static const struct drm_display_mode pdic_display_adv7391_mode = {
      .clock = 27000,
      .hdisplay = 1440,
      .hsync_start = 1440 + 24, //h_active_area + FP
      .hsync_end = 1440 + 24 + 126, //h_active_area + FP + PW
      .htotal = 1440 + 24 + 126 + 138, //h_active_area + FP + PW + BP
      .vdisplay = 288,
      .vsync_start = 288 + 2, //v_active_area + FP
      .vsync_end = 288 + 2 + 3, //v_active_area + FP + PW
      .vtotal = 288 + 2 + 3 + 19, //v_active_area + FP + PW + BP
      .vrefresh = 25,
      };

      static const struct panel_desc pdic_display_adv7391 = {
      .modes = &pdic_display_adv7391_mode,
      .num_modes = 1,
      .bpc = 8,
      .size = {
      .width = 130,
      .height = 98,
      },

      .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
      };

      >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

    • As per Section 2.3.2- provided RGB16 input [ RGB16-565 16-bit data] – 8bit output interface with below changes:

      Below is the dump of the register of DSS system.

      >>>>>>>>>>>>>>>>>>>>>>>>>>

      All values are in HEX.

      DISPC_CONTROL2 00900109

      DISPC_CONFIG2 00000000

      DISPC_OVL_ATTRIBUTES(VID2) 0280840c

      DISPC_DATA_CYCLE1(LCD2) 00000008

      DISPC_DATA_CYCLE2(LCD2) 00000008

      DISPC_DATA_CYCLE3(LCD2) 00000000

    In this case lcd timing will be same just bus format will be change MEDIA_BUS_FMT_RGB888_1X24 to MEDIA_BUS_FMT_RGB565_1X16.

    NOTE: ADV7391 will accept only YCbCr data input interleaved 4:2:2 format over 8-bit bus rate of 27Mhz

  • Hi Pavithra,

    Because of the HSYNC field limitation, 8bit only, we cannot configure DSS to output correct BT656 for getting NTSC/PAL resolution. ADV7393 supports another way to receive data, ie RGB565 on 16bit discrete sync interface. 

    I would suggest you first to check if the new encoder supports this input data interface?

    Regards,

    Brijesh