TMS320VC5401 with external crystal

Andig said:

For the first time, I use a TMS320VC5401 to design an audio amplifier along with an ADC and a DAC.  Say the sample rate is 48KHz (typically for audio processor), how do I choose a value of the external crystal to create vaious internal clock frequency output to BCLKR0 (pin 41 receive clock input), BFSR0 (pin43 frame synchronization pulse receive input) and BCLKX1 (pin49 transmit clock)? Is it doable?

There are a few ways to generate clocks to the ADC and DAC devices.  One method would be to provide the appropriate clock directly to the device and then have those devices generate the appropriate BCLKR and BCLKX bit rates back to the DSP.  The DSP's McBSP interface is flexible to provide the capability of generating the clock frequencies internally to the McBSP or to provide the facility for the clock signals to be generated externally via configuration register bits in the McBSP.  Generally, the types of Analog devices that have this functionality are codecs (ie. ADC and DAC integrated in one device).

However, if you desire or need to generate the clocks inside the DSP and provide the clocks to the ADC and DAC, then you will need to understand the clock generation structure of the DSP.

The crystal will then drive the PLL inside the device.  This will have a particular M (multiplier) and N (divider) ratio to generate the DSP CPU clock.  This is also used as the basis for the reference clock to the McBSP's Sample Rate Generator logic which will drive the BCLKX, BCLKR and BFSR signals.  From the point of the reference clock to the McBSP, everything from that point will be a divide value from the reference frequency.

On the C5401, four different clocks can be the input to the McBSP Sample Rate Generator.  This is described in Table 3-6 of the TMS320VC5401 datasheet (SPRS253).

• CLKS pin
• CPU clock
• BCLKR
• BCLKX

Section 5.5 describes the crystal frequency range supported by the on-chip oscillator.  This is 10MHz <= freq <= 20MHz.  This can then be multiplied up by the PLL but needs to adhere to the maximum operating frequency of the VC5401 of 50MHz.

You can also drive the X2/CLKIN input with an external oscillator, bypassing the internal oscillator, with up to a 50MHz clock input.

You will also need to reference the TMS320C54x DSP Reference Set Volume 5: Enhanced Peripherals (SPRU302).  The bit clocks will be (reference clock)/(1 + CLKGDV).  Therefore,  the BCLKR(X) = CPU clock / (1 + CLKGDV).  The frame sync period is then derived from the CLKG with CLKG/(1 + FPER).

Your 48KHz frame rate is what BFSR needs to be.  Therefore, the frequency of BFSR needs to be (CPU clock) / ((1 + CLKGDV)*(1 + FPER)).
You need to have the BCLKR/X frequency provide for the number of bits of resolution of your ADC and DAC.

Very helpful!  Thanks Brandon.

Regards,

Andig