This question deals with the following Literature:
https://www.ti.com/lit/an/spraar7i/spraar7i.pdf
Page 9:
“Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission lines.”
This comment isn't talking about just nearby the SoC, but the entire trace, right? We want to keep trace width constant to maintain impedance congruity, right?
Page 13/15:
(p13)" TI recommends voiding the SMD mounting pads of the reference plane by 100%."
(p15)“Incorporate 60% voids under the ESD/EMI component signal pads to reduce losses.”
Not sure what the nuance behind "60%" comes from...or the discrepency between one statement regarding 100%, and the other about 60%...?
I saw this stackexchange post that gives an answer I can understand...is this accurate?
Page 15:
“Use 0402 0-Ω resistors for common-mode filter (CMF) no-stuff options because larger components will typically introduce more loss that the CMF itself.”
I don't understand the "no-stuff" comment, or why you use 0Ω resistors (0402)...?
Is this saying during assembly, if you don't populate the CMF, use 0402-size 0Ω resistors? If you use larger-size resistor, then you get similar losses to the CMF, so why not just populate the CMF...right?
Is that what it is saying?
