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AM6526: Questions: High-Speed Interface Layout Guidelines (Rev. I)

Part Number: AM6526

This question deals with the following Literature: 

Page 9:

“Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission lines.”

This comment isn't talking about just nearby the SoC, but the entire trace, right? We want to keep trace width constant to maintain impedance congruity, right?

Page 13/15:

(p13)" TI recommends voiding the SMD mounting pads of the reference plane by 100%."
(p15)“Incorporate 60% voids under the ESD/EMI component signal pads to reduce losses.”

Not sure what the nuance behind "60%" comes from...or the discrepency between one statement regarding 100%, and the other about 60%...?
I saw this stackexchange post that gives an answer I can this accurate?

Page 15:

“Use 0402 0-Ω resistors for common-mode filter (CMF) no-stuff options because larger components will typically introduce more loss that the CMF itself.”

I don't understand the "no-stuff" comment, or why you use 0Ω resistors (0402)...?
Is this saying during assembly, if you don't populate the CMF, use 0402-size 0Ω resistors? If you use larger-size resistor, then you get similar losses to the CMF, so why not just populate the CMF...right?
Is that what it is saying?

  • Attaching "spraar7i Review and Layout Details" checksheet from the customer.
    I hope we can take a look at this and provide some feedback.

    Link to File (TIDrive)

  • Answers:

    1) Yes. On some devices, HS signal escape from the SoC requires that the general trace rules be modified.

    2) The P13 recommendation is specific to the required SMD devices such as the SS AC coupling caps. The P15 recommendation refers to the EMI/ESD components, which are not necessarily required (depending on implementation).

    3) Yes. This recommendation ensures that if a decision is made to remove CMF for SI concerns, that the footprint is such that SI improvement can actually be realized with the bridging resistors.

  • Hi Dave,

    2) I understand voiding is used to increase transmission line impedance under the SMD devices; as their larger pads creates more parasitic capacitance that lowers the line's impedance. For that reason, would you see a risk/issue associated with using 100% voiding under the EMI/ESD components as well? Is the 60% kind of a target-minimum?


  • Darren,

    It really depends on the EMI/ESD devices themselves. I think the risk would be small for a reasonably well designed board, but as always, things like this should be simulated to ensure that there are no surprises.