AM4379: QSPI_CLK

Hi,

So we cann't change the frequency during boot, right？

HI，

The SPI clock generator uses the QSPI_FCLK clock as an input, and generates the qspi1_sclk, which is a divided version of the QSPI_FCLK clock. The divide ratio is a 16-bit value configured through the QSPI_CLOCK_CNTRL_REG[15:0] DCLK_DIV bit field and thus provides a division factor in a range from 1 to 65536. The QSPI_FCLK clock is divided by the DCLK_DIV value + 1 to provide the qspi1_sclk clock. When DCLK_DIV = 0x0 the QSPI_FCLK clock equals the DCLK clock. The value in the DCLK_DIV bit field applies only when the QSPI_CLOCK_CNTRL_REG[31] CLKEN bit is set to 0x1. Figure 27-3 shows the SPI_CLKGEN block.

QSPI_FCLK is 12M or 48M ?  If it is 48M, then the DCLK_DIV of QSPI_CLOCK_CNTRL_REG is 0, CLKEN is 1, and the output qspi1_SCLk should be 48M.

Is the maximum size of qspi1_sclk only 12M?

• Can  qspi1_sclk be set to 48M? How do I set  qspi1_sclk to 48M?  

The subject owner is currently out of the office. Please allow until early next week for a response. Thanks.

Hi，After boot mode, can I change qspi1_SCLK to 48M when entering the application?  How to modify?  thank you 

The DCLK_DIV for QSPI_CLOCK_CNTRL_REG is probably set to 3 in ROM code.  But when you look at the register value with CCS, it always reads 0.  It is an incorrect display.  It might be mistaken for having been set to 0.  It is recommended to add a table in the manual explaining the frequencies corresponding to different DCLK_DIV.