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DRA821U: Processors forum

Deyin Zhang
Prodigy 10 points
Part Number: DRA821U
Other Parts Discussed in Thread: DRA821


DRA821 BSDL file (J7200_DRA821_v1p0), DDR_RET signal PIN must be low level to enter BSDL function.
According to the DEMO reference provided in 2021 (tidm738_SCH), H_DDR_RET_1V1 requires pull-up of 10K to 1.1V; This conflicts with BSDL functionality

  • 0
    TI__Mastermind 39570 points

    DDR Retention Mode is a special low power mode used to keep DDR memory intact while the rest of the device is off, thus it isolates the DDR controller portions from the rest of the processor.  When DDR_RET pin is low, this is the normal mode (no isolation).  When the pin is high, the DDR controller is in retention mode and isolation. As mentioned, for BSDL function there should be no isolation thus DDR_RET pins should be low.

    In most of our solutions, the control for the DDR_RET pin is from the Power Management IC (PMIC). The PMIC's IO is typically open-drain, and that is the reason for the on-board pull-up recommendation.  If DDR_RET is not ever needed, we recommend the pin be pulled low (no pull-up needed in this case.)