TDA3MV: BT.656 output on LCD1 display

Hi SI,

Once we say BT656, videoIfWidth is not really used. But since there is a check inside the driver, which allows only valid videoIfWidth, it fails. Please use 12bit as videoIfWidth, it should be fine.

Regarding BT656 output, please note that DSS outputs 10bit data on D0-D9 data lines for BT656 output format. So if you receiver is using 8bit data, please make sure to use upper 8bit data lines. Also please note that there is a hsync size limitation. I think DSS can support only update 256 clock cycle for the hsync. Please see if these conditions are taken care. 

Regards,

Brijesh

Hi Brijesh,

Except Hsync limitation, we have checked all these with customers already. Do you have any idea how customer can check if their BT656 signal output in DSS is correct?

Thanks and Best Regards,

SI.

Hi SI,

Bit difficult, since embedded syncs. Can we atleast probe the data lines and see if they are toggling? Also please check if pinmux for the data lines are setup.. 

Regards,

Brijesh

Hi Brijesh,

Brijesh Jadav said:

I think DSS can support only update 256 clock cycle for the hsync. Please see if these conditions

Could you please explain this with more details? Their resolution is 640x480. Do you mean only 256, 512, 768 pixels can be supported for horizontal?

Brijesh Jadav said:

Can we atleast probe the data lines and see if they are toggling? Also please check if pinmux for the data lines are setup.. 

Thanks for the response. I'll check it with customers and let me update soon.

Thanks and Best Regards,

SI.

Hi SI,

The size of the field in the register, where we specify hsync length in clock cycles, is just 8bits, so we can have only 256 clock cycles of hsync. This is not sufficient for the 480i, 576i resolution over 8bit interface.. 

Regards,

Brijesh

Brijesh,

Thanks for the confirm. Yes. it should be an issue. 

Could you please provide more details on this? where can I check it in TDA3 TRM?

I checked 9.2.4.13.4. DISPC VP1 BT.656 and BT.1120 Modes and 9.2.4.13.7 DISPC VP1 Timing Generator and Panel Settings, but could not find any limitation for hsync length. I found only 'DISPC_VP1_SIZE_SCREEN[27:16] LPP bit field' which has range from 1 to 4096.

It would be helpful to make customer understand if there is any description for this limitation in the TRM.

And, what is the PCLK of BT656 output in TDA3 LCD1? BT656 standard present 480i, 576i with 27Mhz PCLK as you know, but I'm curious if PCLK is still 27Mhz.

Thanks and Best Regards,

SI.

Hi SI,

Please check HSW field in the  DISPC_VP1_TIMING_H register. This field is just 8bits. I think this limitation is also mentioned in the errata document. 

Yes, pixel clock for 480i and 576i is 27MHz. 

Regards,

Brijesh

Brijesh,

I could not find this limitation in the errata, and I found below CAUTION in the TDA2 TRM.

Is there any way to output BT656 640x480 resolution with embedded sync in LCD1?

I found there is someone implement BT656 1920x720 in TDA2SG in below e2e. Can you guess how they can implement it?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1038316/tda2sg-bt656-output-resolution/3841312?tisearch=e2e-sitesearch&keymatch=bt656%2525252520AND%2525252520dss#3841312

Thanks and Best Regards,

SI.

Hi SI,

Sung-IL said:

I could not find this limitation in the errata, and I found below CAUTION in the TDA2 TRM.

Yes, this is the one i was talking about. 

Sung-IL said:

Is there any way to output BT656 640x480 resolution with embedded sync in LCD1?

Well, as long as HS width is less 256 clock cycle, it is possible to output this resolution.

Regards,

Brijesh

Brijesh,

256 clock cycle means 256 pixels, right?

Thanks and Best Regards,

SI.

Hi SI,

No, this field is in terms of clock cycles, so if we are using BT656, it would be 2 clock cycles per pixel, so 256 pixels would require 512 clock cycles, which is not possible. 

Regards,

Brijesh

Brijesh,

I'm still confused on this. I found below picture in the TDA3/TDA2 TRM and it seems PPL is a pixel number per each line.

As PPL support 12bits(11:0), the maximum pixels per line should be 2048.  I think the limitation of HSW is only applied to BLANKING period.

Could you please double check this again?

As you mentioned, if the horizontal pixel size is limited to 256 clocks(128pixels), even QVGA(320x240) can not be displayed in this case. 

Thanks and Best Regards,

SI.

Hi SI,

Yes, HSW is horizontal sync width, which is part of the horizontal blanking period.

Regards,

Brijesh

Hi Brijesh,

Can you check below register values for BT656 output(640x480) and let me know your opinion on this?

Thanks and Best Regards,

SI.

Hi SI,

Configuration seems to be correct,

- BT656 output is enabled

- Color Space conversion is enabled

- HSW set to 0xFF

- Vertical blanking is set to 0

- VP  enabled

-  VPPROGLINENUMBERMODULO is set, as not required

- Go bit is set

Although, line interrupt is set, i dont see anything in the Line status register. Are you getting anything in the output? Also is the pixel clock running fine for this VP? Do you see Vsync interrupt? 

Regards,

Brijesh