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AM5729: PRU inter-core interrupts

Part Number: AM5729

I am using an AM5729 with kernel 4.19.94-ti-r64 running on the A15s. I have RPmsg configured to communicate with core 0 and core 1 of PRU2. core 0 is doing high speed data acquisition and using XOUT to push data to core 1 to store in physical memory for Linux to process. Since host interrupt 0 and 1 are consumed by the RPMsg interface, how do I configure an additional interrupt to signal PRU2 Core 1 to do the corresponding XIN?

The channel mapping to interrupt setup is not very clear.

AM572x TRM

SPRUHZ6L – October 2014 – Revised August 2019 PRU-ICSS Interrupt Controller Basic Programming Model

I have used pru-software-support-package as the base code for the RPMsg communication with the ARM and this works fine.


I just need some info for configuring the inter-core interrupt signal and mapping, so that I can capture the interrupt. I have seen a few examples of inter-core interrupts, but they are using interrupt host interrupt 0 or 1. When I try this I get an error message during start up the the signal is in use. There has to be a way to map the interrupt, and overlay the existing interrupt (OR'ed together), and some way to determine the source of the interrupt.

any help is greatly appreciated.

  • For anyone looking for an answer using the examples as a base, the following is required to enable and additional interrupt.

    After some experimentation I found the correct process.

    add interrupt entry to resource_table_1.h.  _0.h for core 0 _1.h for core 1.

    struct ch_map pru_intc_map[]

    I added this pair to map int 21 to host interrupt 1

    {21, 1},

    in PRU0 I added,

    #define  PRU0_TO_PRU1_INTERRUPT  21U;

    this line of code triggers the interrupt on PRU second core

    __R31 = (PRU0_TO_PRU1_INTERRUPT - 16) + (1 << 5);

    the R31 write to trigger the interrupt is described in the TRM.

    SPRUHZ6L – October 2014 – Revised August 2019 Event Interface Mapping (R31): PRU System Events.

    on PRU second core you need to check where the interrupt originates. I have RPMsgs from the ARM and interrupts from the the first core

    refer to; PRU-ICSS Interrupt Status Checking

    #define FROM_PRU0_HOST 21U

    if ((CT_INTC.SECR0 & (1 << FROM_ARM_HOST)) != 0)

    // do arm msg processing

    if ((CT_INTC.SECR0 & (1 << FROM_PRU0i_HOST)) != 0)

    // do intercore processing