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PROCESSOR-SDK-AM65X: AM65X and LPDDR4

Marc Murphy
Prodigy 10 points
Part Number: PROCESSOR-SDK-AM65X

Hello

We have created a board design using LPDDR4 and attempting to get signs of life out of the unit.

Using the SDK and the AM65x_DRA80xM_EMIF_Tool_2.02.xlsm spreadsheet we have entered all the relevant timing information to generate the k3-am654-base-board-lpddr4-1600MTs.dtsi

Uboot has been modified to use the newly generated k3-am654-base-board-lpddr4-1600MTs.dtsi

Built using the SDK Makefile with

# make u-boot

# make sysfw-image

Outputted files of:

sysfw-am65x-evm.itb
tiboot3.bin
tispl.bin
uEnv.txt

Written to bootable SD card and used to boot the board.

We can see some clock activity to access the SD card but then it stops.  This happens for both the release image suppled by Ti and our built image.

We understand that the AM65x EVM is DDR4 based and our change is LPDDR4 but need to find a way to ensure the DRAM configuration changes are being applied to the setup with the r5 processor.

Is there currently any known working configuration or image for LPDDR4 and AM65x ?

Thank you

Marc

  • 0
    TI__Guru 54475 points

    Hi Marc,

    I'm looping in my colleague on LPDDR4 support on AM65x.

    Best,

    -Hong

  • 0 in reply to Hong Guan64
    TI__Guru 68950 points

    Please note that AM65x technically does not support LPDDR4 per errata i2231 https://www.ti.com/lit/pdf/sprz452  However, there have been customers that have gotten it to work. 

    Can you post results of the AM65x DDR configuration tool, and can you post a register dump of the AM65x DDR registers (there is a CCS script RegisterDump() to do this)?  Have you attempted to check the DDR interface via CCS and JTAG?  This can help verify the DDR interface without dependency on the rest of the boot.

    Note that from what you described, it still could be a boot issue unrelated to DDR configuration.  The steps above will help narrow down the issue

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 10 points

    Thanks for your feedback James but at the point of design, when we initiallay engaged with Ti the chip was listed as supporing LPDDR4 as detailed in the SPRZ452C–July 2018–Revised September 2019.  This latest errata has been released since the design work was completed and manufacturing started.

    Lets hope that it can be made to work.

    Our module does not have a JTAG interface so unfortunately cannot dump the registers.

    Output from the DDR tool:

    // SPDX-License-Identifier: GPL-2.0+  
    /*      
       * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
       * This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
       * www.ti.com/.../spracj0  
       * Configuration Parameters  
       * Memory Type: LPDDR4  
       * Data Rate: 1600 MT/s
       * ECC Enabled: No  
       * Data Width: 32 bits
     */    
    # define DDR_PLL_FREQUENCY 333000000
    # define DDRSS_V2H_CTL_REG 0x000073FF
    # define DDRSS_DDRCTL_MSTR 0xC3080020
    # define DDRSS_DDRCTL_RFSHCTL0 0x00210070
    # define DDRSS_DDRCTL_ECCCFG0 0x00000000
    # define DDRSS_DDRCTL_RFSHTMG 0x0028007F
    # define DDRSS_DDRCTL_CRCPARCTL0 0x00008000
    # define DDRSS_DDRCTL_CRCPARCTL1 0x1A000000
    # define DDRSS_DDRCTL_CRCPARCTL2 0x0048051E
    # define DDRSS_DDRCTL_INIT0 0x4001028C
    # define DDRSS_DDRCTL_INIT1 0x00420000
    # define DDRSS_DDRCTL_INIT3 0x00240012
    # define DDRSS_DDRCTL_INIT4 0x00180000
    # define DDRSS_DDRCTL_INIT5 0x00100000
    # define DDRSS_DDRCTL_INIT6 0x00550025
    # define DDRSS_DDRCTL_INIT7 0x00000025
    # define DDRSS_DDRCTL_DRAMTMG0 0x0C0E0B0B
    # define DDRSS_DDRCTL_DRAMTMG1 0x00020410
    # define DDRSS_DDRCTL_DRAMTMG2 0x02030809
    # define DDRSS_DDRCTL_DRAMTMG3 0x00505000
    # define DDRSS_DDRCTL_DRAMTMG4 0x05070205
    # define DDRSS_DDRCTL_DRAMTMG5 0x02030505
    # define DDRSS_DDRCTL_DRAMTMG6 0x00000003
    # define DDRSS_DDRCTL_DRAMTMG7 0x00000302
    # define DDRSS_DDRCTL_DRAMTMG8 0x02020C05
    # define DDRSS_DDRCTL_DRAMTMG9 0x40020207
    # define DDRSS_DDRCTL_DRAMTMG10 0x001C180A
    # define DDRSS_DDRCTL_DRAMTMG11 0x1105010E
    # define DDRSS_DDRCTL_DRAMTMG12 0x00020010
    # define DDRSS_DDRCTL_DRAMTMG13 0x0B100002
    # define DDRSS_DDRCTL_DRAMTMG14 0x00000000
    # define DDRSS_DDRCTL_DRAMTMG15 0x00000035
    # define DDRSS_DDRCTL_DRAMTMG17 0x00430022
    # define DDRSS_DDRCTL_ZQCTL0 0x214E000A
    # define DDRSS_DDRCTL_ZQCTL1 0x01127BC8
    # define DDRSS_DDRCTL_DFITMG0 0x04838202
    # define DDRSS_DDRCTL_DFITMG1 0x000C0606
    # define DDRSS_DDRCTL_DFITMG2 0x00000100
    # define DDRSS_DDRCTL_DFIMISC 0x00000005
    # define DDRSS_DDRCTL_ADDRMAP0 0x0000001F
    # define DDRSS_DDRCTL_ADDRMAP1 0x00080808
    # define DDRSS_DDRCTL_ADDRMAP2 0x00000000
    # define DDRSS_DDRCTL_ADDRMAP3 0x00000000
    # define DDRSS_DDRCTL_ADDRMAP4 0x00001F1F
    # define DDRSS_DDRCTL_ADDRMAP5 0x07070707
    # define DDRSS_DDRCTL_ADDRMAP6 0x07070707
    # define DDRSS_DDRCTL_ADDRMAP7 0x00000F0F
    # define DDRSS_DDRCTL_ADDRMAP8 0x00003F3F
    # define DDRSS_DDRCTL_ADDRMAP9 0x00000000
    # define DDRSS_DDRCTL_ADDRMAP10 0x00000000
    # define DDRSS_DDRCTL_ADDRMAP11 0x001F1F00
    # define DDRSS_DDRCTL_DQMAP0 0x00000000
    # define DDRSS_DDRCTL_DQMAP1 0x00000000
    # define DDRSS_DDRCTL_DQMAP4 0x00000000
    # define DDRSS_DDRCTL_DQMAP5 0x00000000
    # define DDRSS_DDRCTL_PWRCTL 0x00000000
    # define DDRSS_DDRCTL_RANKCTL 0x00000000
    # define DDRSS_DDRCTL_ODTCFG 0x04000400
    # define DDRSS_DDRCTL_ODTMAP 0x00000201
    # define DDRSS_DDRPHY_PGCR0 0x87001E00
    # define DDRSS_DDRPHY_PGCR1 0x020046C0
    # define DDRSS_DDRPHY_PGCR2 0x00F04E35
    # define DDRSS_DDRPHY_PGCR3 0x55AA0080
    # define DDRSS_DDRPHY_PGCR6 0x00013001
    # define DDRSS_DDRPHY_PTR2 0x000A3DEF
    # define DDRSS_DDRPHY_PTR3 0x00145856
    # define DDRSS_DDRPHY_PTR4 0x00000536
    # define DDRSS_DDRPHY_PTR5 0x000208D6
    # define DDRSS_DDRPHY_PTR6 0x0170029B
    # define DDRSS_DDRPHY_PLLCR0 0x021c4000
    # define DDRSS_DDRPHY_DXCCR 0x20000038
    # define DDRSS_DDRPHY_DSGCR 0x02A0C129
    # define DDRSS_DDRPHY_DCR 0x0000040D
    # define DDRSS_DDRPHY_DTPR0 0x04160905
    # define DDRSS_DDRPHY_DTPR1 0x281B040A
    # define DDRSS_DDRPHY_DTPR2 0x00644103
    # define DDRSS_DDRPHY_DTPR3 #VALUE!
    # define DDRSS_DDRPHY_DTPR4 0x00FE0707
    # define DDRSS_DDRPHY_DTPR5 0x0E1F0905
    # define DDRSS_DDRPHY_DTPR6 0x00000505
    # define DDRSS_DDRPHY_ZQCR 0x0089EC58
    # define DDRSS_DDRPHY_ZQ0PR0 #N/A
    # define DDRSS_DDRPHY_ZQ1PR0 0x00009799
    # define DDRSS_DDRPHY_MR0 0x00000000
    # define DDRSS_DDRPHY_MR1 0x00000024
    # define DDRSS_DDRPHY_MR2 0x00000012
    # define DDRSS_DDRPHY_MR3 #N/A
    # define DDRSS_DDRPHY_MR4 0x00000000
    # define DDRSS_DDRPHY_MR5 0x00000000
    # define DDRSS_DDRPHY_MR6 0x00000000
    # define DDRSS_DDRPHY_MR11 0x00000055
    # define DDRSS_DDRPHY_MR12 0x00000025
    # define DDRSS_DDRPHY_MR13 0x00000000
    # define DDRSS_DDRPHY_MR14 0x00000025
    # define DDRSS_DDRPHY_MR22 0x00000000
    # define DDRSS_DDRPHY_VTCR0 0xF3C32025
    # define DDRSS_DDRPHY_DX8SL0PLLCR0 0x021c4000
    # define DDRSS_DDRPHY_DX8SL1PLLCR0 0x021c4000
    # define DDRSS_DDRPHY_DX8SL2PLLCR0 0x021c4000
    # define DDRSS_DDRPHY_DTCR0 0x8000B1C7
    # define DDRSS_DDRPHY_DTCR1 0x00030232
    # define DDRSS_DDRPHY_ACIOCR0 0xF0070000
    # define DDRSS_DDRPHY_ACIOCR3 0x00000001
    # define DDRSS_DDRPHY_ACIOCR5 0x09000000
    # define DDRSS_DDRPHY_IOVCR0 0x0F9E9E9E
    # define DDRSS_DDRPHY_DX0GCR0 0x00000000
    # define DDRSS_DDRPHY_DX0GCR1 0x00000000
    # define DDRSS_DDRPHY_DX0GCR2 0x00000000
    # define DDRSS_DDRPHY_DX0GCR3  0x00000000
    # define DDRSS_DDRPHY_DX1GCR0 0x00000000
    # define DDRSS_DDRPHY_DX1GCR1 0x00000000
    # define DDRSS_DDRPHY_DX1GCR2 0x00000000
    # define DDRSS_DDRPHY_DX1GCR3 0x00000000
    # define DDRSS_DDRPHY_DX2GCR0 0x40700204
    # define DDRSS_DDRPHY_DX2GCR1 0x00007FFF
    # define DDRSS_DDRPHY_DX2GCR2 0x00000000
    # define DDRSS_DDRPHY_DX2GCR3  0xFFC0010B
    # define DDRSS_DDRPHY_DX3GCR0 0x40700204
    # define DDRSS_DDRPHY_DX3GCR1 0x00007FFF
    # define DDRSS_DDRPHY_DX3GCR2 0x00000000
    # define DDRSS_DDRPHY_DX3GCR3  0xFFC0010B
    # define DDRSS_DDRPHY_DX4GCR0 0x40703220
    # define DDRSS_DDRPHY_DX4GCR1 0x55556000
    # define DDRSS_DDRPHY_DX4GCR2 0xAAAA0000
    # define DDRSS_DDRPHY_DX4GCR3  0xFFE18587
    # define DDRSS_DDRPHY_DX0GCR4 0x0E00123C
    # define DDRSS_DDRPHY_DX1GCR4 0x0E00123C
    # define DDRSS_DDRPHY_DX2GCR4 0x0E00123C
    # define DDRSS_DDRPHY_DX3GCR4 0x0E00123C
    # define DDRSS_DDRPHY_DX4GCR4 0x0E00123C
    # define DDRSS_DDRPHY_PGCR5 0x01010004
    # define DDRSS_DDRPHY_DX0GCR5 0x00001919
    # define DDRSS_DDRPHY_DX1GCR5 0x00001919
    # define DDRSS_DDRPHY_DX2GCR5 0x00001919
    # define DDRSS_DDRPHY_DX3GCR5 0x00001919
    # define DDRSS_DDRPHY_DX4GCR5 0x00001919
    # define DDRSS_DDRPHY_DX0GTR0 0x00020002
    # define DDRSS_DDRPHY_DX1GTR0 0x00020002
    # define DDRSS_DDRPHY_DX2GTR0 0x00020002
    # define DDRSS_DDRPHY_DX3GTR0 0x00020002
    # define DDRSS_DDRPHY_DX4GTR0 0x00020002
    # define DDRSS_DDRPHY_ODTCR 0x00010000
    # define DDRSS_DDRPHY_DX8SL0IOCR 0x79000000
    # define DDRSS_DDRPHY_DX8SL1IOCR 0x79000000
    # define DDRSS_DDRPHY_DX8SL2IOCR 0x79000000
    # define DDRSS_DDRPHY_DX8SL0DXCTL2 0x001C1800
    # define DDRSS_DDRPHY_DX8SL1DXCTL2 0x001C1800
    # define DDRSS_DDRPHY_DX8SL2DXCTL2 0x001C1800
    # define DDRSS_DDRPHY_DX8SL0DQSCTL 0x01264310
    # define DDRSS_DDRPHY_DX8SL1DQSCTL 0x01264310
    # define DDRSS_DDRPHY_DX8SL2DQSCTL 0x01264310

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    It looks like there are several issues with the config.  Can you send the full spreadsheet that was used for this configuration?  And the DDR datasheet for the device you are using?

    Also, when you attempt to boot, can you probe DDR CKE and DDR RESET signals?  What do those look like during boot?  This will determine if you are even getting to the DDR initialization

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 10 points

    We have scoped the DDR CKE and DDR RESET signals at boot attempt and both show no activity.

    Link to retrieve the spreadsheet with the values we have populated from the DDR datasheet here:

    AM65x_DRA80xM_EMIF_Tool_2.02.xlsm

    Link to the DDR datasheet here:

    MT53E768M32D4DT-053 AIT:E

    Thanks

    Marc

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    Thanks, Marc.  If CKE and RESET remain low during boot, then the problem is occurring before DDR initialization.  

    Does the same SD card work on one of our EVMs?  Can you compare the EVM vs your board design around the SD card circuitry to ensure similarity.  Check basic things like clocks, power, resets etc.  I think the problem is the initial download of the bootloader from the SD card to internal memory.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 10 points

    Hi James

    SD card connection is the same as the reference design. CPU clock and power rails are present and correct. CPU is out of reset. We have taken some scope traces of the SD card with the card loaded with our image and we can see the CPU talking to the card, doing initialisation (have manually decoded the data on the CMD line to see what is being sent/read) and loading data.

    We have a AM65xx eval board coming from a customer to allow us to test further. We also have a logic analyser on route which supports SD card protocol decode to check what is actually being loaded.

    It looks to me that the CPU is checking pin straps (which are set to boot from SD card), initialising the card, loading data into internal cache then either failing to execute what has been loaded, what has been loaded is garbage or what has been loaded from the card is not suitable for the CPU to execute and boot.

    Thanks

    Marc

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    Marc, thanks for the update.  keep me posted.

    James

  • 0 in reply to JJD
    Prodigy 10 points

    Hi James

    We have received the logic analyser and the AM65xx eval board. Looking at the SD card signals with protocol decoder it all looks correct. We can see messages sent to/from CPU and SD card along with blocks of data being loaded from the board.

    With the eval board we see the same thing and looking at the UART ports I noticed that the eval board gives some debug on the MCU part 1 port, see below.

    üspl_load_image_fat: error reading image sysfw.itb, err - -2
    Error -2 occurred during loading SYSFW image!

    resetting ...
    k3-secure-proxy secproxy@28380000: k3_sec_proxy_send: Thread8 verification failed. ret = -61
    ti_sci dmsc: ti_sci_do_xfer: Message sending failed. ret = -61
    ti_sci dmsc: Mbox communication fail -61
    k3-secure-proxy secproxy@28380000: k3_sec_proxy_send: Thread8 verification failed. ret = -61
    ti_sci dmsc: ti_sci_do_xfer: Message sending failed. ret = -61
    ti_sci dmsc: Mbox communication fail -61
    k3-secure-proxy secproxy@28380000: k3_sec_proxy_send: Thread8 verification failed. ret = -61
    ti_sci dmsc: ti_sci_do_xfer: Message sending failed. ret = -61
    ti_sci dmsc: Mbox communication fail -61
    System reset not supported on this platform
    ### ERROR ### Please RESET the board ###

    We do not see any debug from the main UART 0 port.

    Looking at the same UART on our board booting the same image I see the same debug. We need to build a suitable image for the eval board, the message above is for LPDDR4 RAM config. Checking the SD card I notice the .itb file name was different to the one in the debug above. After I renamed the file on the SD card I no long get any debug on the MCU UART port.

    I do see some debug on UART 0.

    U-Boot SPL 2021.01-g44a87e3ab8 (Mar 24 2022 - 03:18:28 +0000)
    SYSFW ABI: 3.1 (firmware rev 0x0016 '22.1.1--v2022.01 (Terrific Llam')
    Reading on-board EEPROM at 0x50 failed -1
    read_dqs_training:ERROR: Read DQS Gate training failed
    DRAM init failed: -22

    resetting ...

    A step closer as at lease the CPU is running the SD card image. The CPU keeps resetting printing the debug above. Clearly something on the DDR side of things is not happy.

    Thanks

    Marc

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    Marc, yes, now it looks like it is getting stuck in the LPDDR4 training.  Can you confirm the CKE and RESET signals as mentioned before? 

    I will need some time to check your configuration.

    REgards,

    James

      

  • 0 in reply to JJD
    Prodigy 10 points

    Hi James

    I can confirm we see activity on the DDR CKE and RESET lines. RESET keeps resetting the DRAM as the debug prints out resetting.

    Regards

    Marc

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    Marc, can you zip up the xls and directly attach it here.  I cannot access the google drive from inside our firewall.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 10 points

    Hi James, I cant see a way to attach a zip file to the post.  It has to be via a hyperlink.

    If you want to PM me your email address I can send over as an attachment.

    Regards

    Marc

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    when replying to the thread, hit "Insert", "Image video file", then "Upload" (it looks greyed out, but it will bring up an explorer window to choose a file.

    Regards,

    James

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    Marc, sorry for the delay here.  Should be able to look at this tomorrow.

    James

  • 0 in reply to JJD
    TI__Guru 68950 points

    Marc, there were several errors in the spreadsheet based on the device you pointed to.  I've attached the updated spreadsheet.  If you have any questions on how i filled it out, let me know.  Please try with the output file from the new spreasheet

    Also, i noticed you pointed to a non power of 2 device (24Gb total density).  Is this the device you are using?  The spreadsheet doesn't support this size of memory, so there may be some addressing issues to work out.

    /cfs-file/__key/communityserver-discussions-components-files/791/AM65x_5F00_DRA80xM_5F00_EMIF_5F00_Tool_5F00_2.02_5F00_TIedits.xlsm.zip

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 10 points

    Hi James, We have used the values provided in the spreadsheet to rebuild uboot and attempted boot again.  Still no joy.

    You are correct about the part being a 24Gb/3GB density, would this cause an issue ?

    Do you require any debug information to assist in identifying the boot/initialisation issue ?

    Regards

    Marc

  • 0 in reply to Marc Murphy
    TI__Guru 68950 points

    yes, the non-power of two device might throw another wrinkle into the problem.  Let's try to simplify the issue to see if we can get any accesses working.  I've attached another configuration which just configures the device as a x16, single channel, signal rank memory, so just trying to exercise one die.  Based on your part number, you have a device with 4die, total of 24Gb, so each die should be 6Gb.  To keep it power of two, i just configured 4Gb of memory.  I additionally lowered the frequency to 533MHz.

    There was also a bug i noticed in the spreadsheet.  It looks like you had the output driver impedance of AM65x set to 34.3 ohms, and this was producing a couple of NA in the formulas.  I fixed this in the attached spreadsheet.

    Since you don't have JTAG, you may have to modify the initialization driver to output values to a terminal or something.  A couple of items to output:

    -the full register dump (controller and PHY) after init has completed

    -A few write then read accesses to DDR memory after init has completed, to see if there is any success in data accesses.

    Regards,

    James

    /cfs-file/__key/communityserver-discussions-components-files/791/AM65x_5F00_DRA80xM_5F00_EMIF_5F00_Tool_5F00_2.021_5F00_TIedits.xlsm.zip