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PROCESSOR-SDK-AM64X: How to clear the contents of the BS RAM in a single instruction

MK
Intellectual 980 points
Part Number: PROCESSOR-SDK-AM64X

Hi team,

I have to reuse my BS-RAM memory after a computation. The only way I can clear the sheets is by the following code -

clear_bs .macro P
    xout  0x1E, &R10, 2
    loop EndLoop, P
        xout 0x1E, &R2, 32
        add  r10,r10, 1
        xout 0x1E, &r10, 2
EndLoop:

This typically takes 6 cycles or more. I would like to do this similar to zero &r2, 120 instruction where al the registers are cleared in one go.

Can you help me determine if a similar instruction can accomplish this to clear the BS_RAM sheets?

Additionally: Can I access the BS_RAM using the R5 core just to clear the sheets/ Reset BS-RAM  memory?

Best Regards,

Madhurya

  • 0
    TI__Genius 11970 points

    Dear Madhurya,

    Thanks for your query. Let me review the query internally with the team and get back to you.

    Regards

    Anshu

  • 0 in reply to Anshu Choudhary
    TI__Intellectual 980 points

    Hello Anshu,
    Any advice here?

    Best Regards,

    Madhurya

  • 0 in reply to MK
    TI__Intellectual 980 points

    Hi Anshu,

    I'm still struggling with clearing the BS-RAM sheets with less instructions. I was wondering if there is a reset option available?
    Let me know if you have any ideas here!

    Best Regards,

    Madhurya 

  • 0 in reply to MK
    TI__Genius 11970 points

    Madhurya ,

    apologies for the delay, while i get the answer for the Query let me pointy you to a FAQ on Latencies here 

    Ragards

    Anshu

  • 0
    TI__Guru 72195 points

    Hello Madhurya,

    The PRU broadside RAM is only accessible from the PRU core that it is attached to. Other cores are unable to view and modify it (the R5Fs, other PRU cores, etc). That is why you cannot see the PRU broadside RAM directly from CCS, since the CCS debugger does not have visibility into that memory space.

    1) To confirm: Are you doing
    Write computation values to BS RAM --> zero out computation values to BS RAM (shown above) --> Write new computation values to BS RAM?

    If so, is there a particular reason you need to zero out the memory before writing new values to the BS RAM, or can you just drop that step?

    2) It looks like you would be able to just set AutoIndexEn = 1h, as per the AM64x TRM section "Programming the BS RAM". In that case, I would expect your code to look like this:

    clear_bs .macro P
    xout  0x1E, &R10, 2
    loop EndLoop, P
        xout 0x1E, &R2, 32
        ; if the values in R2-R9 need to be updated, do that here
EndLoop:

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Intellectual 980 points

    Hi Nick!

    1) To confirm: Are you doing
    Write computation values to BS RAM --> zero out computation values to BS RAM (shown above) --> Write new computation values to BS RAM?

    If so, is there a particular reason you need to zero out the memory before writing new values to the BS RAM, or can you just drop that step? Yes, but not LDI or MOV; I'm using the Add instructions. Hence I need to clear my BS-RAM sheets to do my new computation since it adds to it.

    2) It looks like you would be able to just set AutoIndexEn = 1h, as per the AM64x TRM section "Programming the BS RAM". In that case, I would expect your code to look like this
    This code only clears the BS_RAM sheet 1, does AutoIndexEn = 1h clear all the sheets?

    Best Regards,

    Madhurya

  • 0 in reply to MK
    TI__Guru 72195 points

    Hello Madhurya,

    Please take another look at the TRM section I pointed to:

    AutoIndexEn

    When enabled, each PRU or RTU_PRU core’s write or read to the BS
    RAM will cause the RAM_Address to increment by 1.
    Note: Each increment of the RAM_Address is the equivalent of 32
    Bytes. The next read or write address will always be 32 Bytes later,
    regardless of the read or write data size. Rollovers of RAM_Address are
    not supported. Firmware must reset RAM_Address to zero. This mode
    must be set before RAM Data transaction.

    Regards,

    Nick