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[FAQ] AM6442: How to configure the GPIO interrupt

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

This FAQ Describes how to configure GPIO Interrupt for different Cores and created different examples on different Cores.

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  • AM64x GPIO Overview

    What is GPIO?

    The General-Purpose Input/output (GPIO) peripheral provides dedicated general-purpose pins that can be

    configured as either inputs or outputs.

    GPIO can be used in three modes: Input / Output / Interrupt

    GPIO’s availability in the AM64X SDK:

    The device has three instances of GPIO modules. The GPIO pins are grouped into banks (16 pins per bank and 9 banks per module), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since MCU_GPIO0[23:143], GPIO0[87:143], and GPIO1[88:143] are reserved in this device, general purpose interface supports up to 198 pins.

    GPIO Interrupt Connectivity in AM64X SDK:

    Because this device muxes GPIO signals with other functional signals, the availability of any particular GPIO and hence the usability of its associated interrupt will change based on the use case pin muxing. The large number of possible GPIO interrupt sources makes it impractical to route all interrupt events to each processing element. Since most applications do not typically require a large number of GPIO interrupts, the interrupt uncertainty is resolved by mapping all GPIO interrupts to a series of event muxes implemented using Interrupt Router (IntRouter) modules. These muxes allow any one of the available GPIO interrupts to be selected and passed on as an event to the various processor interrupt controllers and DMA controllers. Event selection is controlled through associated registers within each IntRouter.

    The GPIO bank interrupts already represent a consolidation of the 16 GPIO interrupts associated with each bank and are routed directly to various interrupt controllers rather than through the GPIO IntRouters.

    One of the GPIO pins has a potential use case as an Arm reset input and should therefore be routed as highest priority interrupt in the GIC and mapped to nFIQ in software.

    Figure 1. MCU_GPIO Interrupt Router Connectivity

    Figure 2. MAIN_GPIO Interrupt Router Connectivity

    Fig 3: GPIOMUX_INTRTR0 Integration on MCU Domain.

    Fig 4. GPIOMUX_INTRTR0 Integration on Main Domain.

    Procedure for GPIO Interrupt configurations

    1. GPIO configuration: Do the system config as per the your GPIO requirement.

    2. Interrupt Router Configuration: Configure the Interrupt Router output based on Destination core. This information is not configurable in system config as of now. This will be implemented in next releases.

    Since the router information is not configurable in system config currently, please follow the below procedure to configuring interrupt router output manually.

  • Configuring Interrupt Router Output manually

    Example: Configuring GPIO Interrupt for GPIO0_63 on R5FSS_0 core.

    Please check the sciclient_defaultBoardcfg_rm.c file and find it in below path


    <MCU+SDK Install Location>\source\drivers\sciclient\sciclient_default_boardcfg\am64x_am243x.

     

    1. In above example we have selected MCU_GPIO0_63 Pin for interrupt and all interrupts of GPIO’s belongs to TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 router and the selected destination core as R5FSS_0.
    2. We can select MAIN_GPIO_MUX_INTROUTER0_OUTP from 0 to 15. But only 2(num_resource) resources are allocated under the TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 router in TISCI_HOST_ID_MAIN_0_R5_0 core and Interrupt Router output should be start from 8 only because start_resource is starting from 8.

            {

                .num_resource = 2,

                .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,  TISCI_RESASG_SUBTYPE_IR_OUTPUT),

                .start_resource = 8,

                .host_id = TISCI_HOST_ID_MAIN_0_R5_0,

            },

     

    1. So, we can put the Interrupt router output as 8 or 9 and destination core is R5FSS_0.

  • Example 1: Configuring GPIO Interrupt for GPIO0_63 on R5FSS_1 core with FREE RTOS

    Step 1: use Sysconfig to config GPIO

     .

    Step 2: Include board.c file in your workspace and which is available at path. <MCU+SDK Install Dir>\examples\drivers\gpio\gpio_input_interrupt\am64x-evm\r5fss0-0_nortos.

    In the above example we have selected MCU_GPIO0_63 Pin for interrupt and the destination core is R5FSS_1.

    Step 3: There are 2 resources that are allocated under the TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 router in R5FSS_1 core and Interrupt Router output should start from 10.

            {

                .num_resource = 2,

                .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),

                .start_resource = 10,

                .host_id = TISCI_HOST_ID_MAIN_0_R5_3,

            },

    So, we can assign the Interrupt Router output (start_resourceas 10 or 11.

    Step 4: Finally, we need to update below Macro’s in board.c file

        #define BOARD_BUTTON_GPIO_INTR_NUM CSLR_R5FSS0_CORE1_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_10 or CSLR_R5FSS0_CORE1_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_11
        b.rmIrqReq.src_id                 = TISCI_DEV_GPIO0;

        rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO0 +  GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);

        rmIrqReq.dst_id                     = TISCI_DEV_R5FSS0_CORE1;

    Step5: Call Board_gpioInit () before GPIO initializations

    Step 6 : Compile code and Load binaries on R5FSS_1 core

  • Example 2: Configuring GPIO Interrupt for GPIO0_63 on R5FSS_0 core with FREE RTOS

    Step 1: use Sysconfig to config GPIO <Same as above>

    Step 2: Include board.c file in your workspace and which is available at path. <MCU+SDK Install Dir>\examples\drivers\gpio\gpio_input_interrupt\am64x-evm\r5fss0-0_nortos. <Same as above>

    Step 3: There are 2 resources that are allocated under the TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 router in R5FSS_0 core and Interrupt Router output should start from 8.

            {

                .num_resource = 2,

                .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),

                .start_resource = 8,

                .host_id = TISCI_HOST_ID_MAIN_0_R5_0,

            },

    So, we can assign the Interrupt Router output (start_resourceas 8 or 9.

    Step 4: Finally, we need to update below Macro’s in board.c file\

        #define BOARD_BUTTON_GPIO_INTR_NUM CSLR_R5FSS0_CORE1_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_8 or CSLR_R5FSS0_CORE1_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_9
        b.rmIrqReq.src_id                 = TISCI_DEV_GPIO0;

        rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO0 +  GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);

        rmIrqReq.dst_id                     = TISCI_DEV_R5FSS0_CORE0;

    Step5: Call Board_gpioInit () before GPIO initializations

    Step 6 : Compile code and Load binaries on R5FSS_0 core

  • Example 3: Configuring GPIO Interrupt for GPIO0_43 on R5FSS_1 core with FREE RTOS

    Step 1: use Sysconfig to config GPIO 

    Step 2: Include board.c file in your workspace and which is available at path. <MCU+SDK Install Dir>\examples\drivers\gpio\gpio_input_interrupt\am64x-evm\r5fss0-0_nortos. <Same as above>

    Step 3: There are 2 resources that are allocated under the TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 router in R5FSS_1 core and Interrupt Router output should start from 10.

            {

                .num_resource = 2,

                .type = TISCI_RESASG_UTYPE (TISCI_DEV_MAIN_GPIOMUX_INTROUTER0, TISCI_RESASG_SUBTYPE_IR_OUTPUT),

                .start_resource = 10,

                .host_id = TISCI_HOST_ID_MAIN_0_R5_3,

            },

    So, we can assign the Interrupt Router output (start_resourceas 10 or 11.

    Step 4: Finally, we need to update below Macro’s in board.c file\

        #define BOARD_BUTTON_GPIO_INTR_NUM CSLR_R5FSS0_CORE1_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_10 or CSLR_R5FSS0_CORE1_INTR_MAIN_GPIOMUX_INTROUTER0_OUTP_11
        b.rmIrqReq.src_id                 = TISCI_DEV_GPIO0;

        rmIrqReq.src_index              = TISCI_BANK_SRC_IDX_BASE_GPIO1 +  GPIO_GET_BANK_INDEX(GPIO_PUSH_BUTTON_PIN);

        rmIrqReq.dst_id                     = TISCI_DEV_R5FSS0_CORE1;

    Step5: Call Board_gpioInit () before GPIO initializations

    Step 6 : Compile code and Load binaries on R5FSS_1 core