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BOOST5545ULP: Not working stereo in AudioCodec_DMA from example library c55_csl_3.08.01

Part Number: BOOST5545ULP


Hi,

I uploded on BOOST5545ULP board an example- AudioCodec_DMA. In this example are both codec and I2S interface prepared for stereo mode. But when I started tetsting board, playing stereo tests thru analog input, in my headphones I heard sound only in left channel. In right channel I could hear only noise. Changing the input channel caused only volume change in my left headphone. Rigth one was still noisy.

What could be a reason for this boards misbehavior?

Thank You in advance.

  • Hi Pawel,

    The CSL for C55x is built for C5517 by default. For C5545, you will need to change the PART2 of csl_general.h so that the CHIP_C5545 is defined. You will need to re-build the csl library and the example after you made the changes.

    Best regards,

    Ming

  • I did exactly what You recommended me, but it gave no improvement. In csl_general.h I have only good defines #define CHIP_C5545 and #define C5545_BSTPCK. I also rebuilt whole project. Unfortunately it did not help.

    What can I do next? Maybe should I change something in project properties or target configuration? 

  • Hi Pawel,

    You will need to rebuild the CSL library project first, then rebuild the I2S example project.

    Best regards,

    Ming

  • Can You explain me how to rebuild whole csl library? I added all project once more and I built them all but it still does not help. Rebuild of library means probably something other than what I did.

  • Hi Pawel,

    Did you re-build C55XXCSL_LP which is the CCS project for CSL library?

    Best regards,

    Ming 

  • I took the following steps:

    1) in cls_general.h I changed defines on #define CHIP_C5545 and #define C5545_BSTPCK

    2) I rebuilt C55XXCSL_LP

    3) I rebuilt CSL_I2S_AudioCodec_DMA

    4) I uploded code into my board

    I had still problem with audio in right headphones channel.

    5) I added in project properties Build/Dependencies C55XXCSL_LP

    Now I have problems with linker:

    'Building target: CSL_I2S_AudioCodec_DMA.out'
    'Invoking: C5500 Linker'
    "C:/ti/ccsv6/tools/compiler/c5500_4.4.1/bin/cl55" -v5515 --memory_model=large -g --define="_DEBUG" --define=c5515 --diag_warning=225 --gen_func_subsections=on --ptrdiff_size=16 --algebraic --asm_source=algebraic -z -m"CSL_I2S_AudioCodec_DMA.map" --stack_size=0x200 --heap_size=0x400 -i"C:/ti/ccsv6/tools/compiler/c5500_4.4.1/lib" -i"C:/ti/c55_lp/c55_csl_3.08.01/build" -i"C:/ti/ccsv6/tools/compiler/c5500_4.4.1/include" -i"C:/ti/bios_5_42_02_10/packages/ti/rtdx/lib/c5500" -i"C:/ti/bios_5_42_02_10/packages/ti/bios/lib" -i"C:/ti/c55_lp/c55_csl_3.08.01/ccs_v6.x_examples/C55XXCSL_LP" -i"C:/ti/c55_lp/c55_csl_3.08.01/ccs_v6.x_examples/i2s/CSL_I2S_AudioCodec_DMA" --reread_libs --warn_sections --xml_link_info="CSL_I2S_IdleLoop_Out_linkInfo.xml" --rom_model --sys_stacksize=0x200 -o "CSL_I2S_AudioCodec_DMA.out" "./AudioCodec_DMA.obj" "./codec_aic3254.obj" "./csl_i2c_ioExpander.obj" "./pll_control.obj" "../C5515.cmd"  -l"Debug/C55XXCSL_LP.lib" -l"libc.a" 
    <Linking>
    warning: creating output section ".inputDataBufLeft" without a SECTIONS
       specification
    warning: creating output section ".inputDataBufRight" without a SECTIONS
       specification
    warning: creating output section ".switch" without a SECTIONS specification
    "../C5515.cmd", line 74: error: program will not fit into available memory.
       placement with alignment/blocking fails for section ".text" size 0x98df page
       0.  Available memory ranges:
       DARAM1       size: 0x2000       unused: 0x2000       max hole: 0x2000    
    "../C5515.cmd", line 80: error: program will not fit into available memory.
       run placement with alignment/blocking fails for section ".bss" size 0x2f0c
       page 0.  Available memory ranges:
       DARAM5       size: 0x2000       unused: 0x2000       max hole: 0x2000    
    "../C5515.cmd", line 72: error: program will not fit into available memory.
       placement with alignment/blocking fails for section "vectors" size 0x200
       page 0.  Available memory ranges:
       VECS         size: 0x100        unused: 0x100        max hole: 0x100     
    error: errors encountered during linking; "CSL_I2S_AudioCodec_DMA.out" not
       built
    
    >> Compilation failure
    gmake: *** [CSL_I2S_AudioCodec_DMA.out] Error 1
    gmake: Target `all' not remade because of errors.

     I think the problem is that in project I have C5515.cmd and I invoke gmake with flag -v5515. It probably happend because in Target Configuration I selected Spectrum Digital C5515 USB Stick. But in the list I can not find C5545.

    How can I correctly set this project for my board?

  • Hi Pawel,

    The line-in loopback for C5545 BP is in C:\ti\c55_lp\c55_csl_3.08.01\demos\out_of_box\c5545\c5545bp_software_01.01.00.00\source_code\c55xx_diagnostics\board\diag\build\boostC5545\audio_line_in_loopback_test. The I2S example is designed for the C5515/C5517 EVM.

    I have tested it on the C5545 BP. the line-in loopback works as expected (both channels).

    Best regards,

    Ming

  • The above example will loopback the line-in audio source for 5 seconds after about 15 seconds wait, so be patient. You can also change the loopback time from 5 sec to 100 sec.

    Best regards,

    Ming

  • Thank You for help. I have still two question.

    1) Can I use headers and source files from csl library on my board? Or are they not prepared for c5545?

    2) How can I program interrupts on my board? In projects for other boards are used vector file in assembly. Does this system work either on BOOST5545ULP?

  • Hi Pawel.

    1) Yes, you can still use the C55x CSL library for C5545, because it is almost the same as the C5515/C5505, except no EMIF. C5517 on the other hand has some differences like I2S and HPI. The reason that the I2S example does not work on C5545 BP is mainly due to the Audio Codec and I2S settings.

    2) The Interrupts are programed the same way for all low power C55x DSPs (C5545/C5515/C5505/C5535/C5517)   

    Best regards,

    Ming

  • Unfortunately I have one more problem. I hope this will be the last. I will create project outside csl_librarys. One folder with all dependeces for user which does not have csl_library on his computer. So I made a new project in CCS11, copied folders with inc and src from csl. In .project file in linkedResources section I added all .c files from src. But when I was trying build my project, all includes were starting compiling also .asm vector files, what caused errors like:

    >> Compilation failure
    src/subdir_rules.mk:9: recipe for target 'src/csl_dma.obj' failed
    "../src/csl_dma.c", line 62: fatal error #5: could not open source file "csl_dma.h"
    1 fatal error detected in the compilation of "../src/csl_dma.c".

    or

    "..\src\csl_irqplug.asm", ERROR!   at line 85: [E9999] Syntax Error
    	      dbl(*SP(#IsrAddr)) = AC0         ; Store ISR function address
     
    "..\src\csl_irqplug.asm", ERROR!   at line 85: [E9999] Invalid mnemonic
                                                           specified
    	      dbl(*SP(#IsrAddr)) = AC0         ; Store ISR function address

    How can I fix this errors? Or maybe there is a better way to realise my idea? Project "all in one folder" will be for me and for further work very useful.

  • Hi Pawel,

    The first error was caused by the lacking of the C:\ti\c55_lp\c55_csl_3.08.01\inc in the including path in your CCS project.

    The second error was caused by the incorrect "assembly source language". It should be "algebraic"

    Best regards,

    Ming

  • Thank You. I really appreciate Your help. Without it, I would probably spend many days struggling with these problems.

    Best regards.

    Pawel Tumialis.

  • I will not create new forum question but i still have problem with DMA. Despite the setting DMA registers properly (I hope so) module does not transfer data from I2S to my array. I know that I have good destination and source address, interrupt function also works. But still my array is empty. What did I wrong? Below I insert my code with screenshots from debug mode.

    Uint16 i2sDmaReadBufLeft[1024]; //my array
    Uint16 Test=0;  //variable for testing interrupt
    
    // in main I call function initialize_dma
    // codec works properly, I show this on a screenshot
    
    TEST_STATUS initialize_dma(void){
        status = DMA_init();
        //Config left read
        dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
        dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;
        dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;
        dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;
        dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S2_TX;
        dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;
        dmaConfig.chanDir      = CSL_DMA_READ;
        dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;
        dmaConfig.dataLen      = 1024;
        dmaConfig.srcAddr      = (Uint32)&CSL_I2S2_REGS->I2SRXLT1;
        //dmaConfig.destAddr       = (Uint32)(i2sDmaReadBufLeft); this gives random address
    
        IRQ_globalDisable();
        IRQ_clearAll();
        IRQ_disableAll();
        IRQ_setVecs((Uint32)&VECSTART);
        IRQ_clear(DMA_EVENT);
        IRQ_plug (DMA_EVENT, &dma_isr);
        IRQ_enable(DMA_EVENT);
        IRQ_globalEnable();
    
        dmaHandleRxL = DMA_open((CSL_DMAChanNum)6,&dmaObj, &status);
        status = DMA_config(dmaHandleRxL, &dmaConfig);
    
        Uint32 buffor = (Uint32)i2sDmaReadBufLeft;  //adding properly address manually
        dmaHandleRxL->dmaRegs->DMACH2DSAL = (Uint16)(buffor);
        dmaHandleRxL->dmaRegs->DMACH2DSAU = (Uint16)(buffor >> 16);
        
        //start channel with sync
        dmaHandleRxL->dmaRegs->DMACH2TCR2 |= 0x8004;
        return (status);
    }
    
    interrupt void dma_isr(void)
    {
        int ifrValue;
    
        ifrValue = CSL_SYSCTRL_REGS->DMAIFR;
        CSL_SYSCTRL_REGS->DMAIFR |= ifrValue;
        Test++;
    }
        

    I2S Configuration

    DMA1 ConfigurationDMA1 Trigger ConfigurationArray is still empty but Test is incremented in interrupt.

  • Hi Pawel,

    Since you are configuring the I2S Read, I think the dmaConfig.dmaEvt should be CSL_DMA_EVT_I2S2_RX instead of CSL_DMA_EVT_I2S2_TX:

    //Config left read
    dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
    dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
    dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
    dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
    dmaConfig.dmaEvt = CSL_DMA_EVT_I2S2_TX;
    dmaConfig.dmaInt = CSL_DMA_INTERRUPT_ENABLE;
    dmaConfig.chanDir = CSL_DMA_READ;
    dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
    dmaConfig.dataLen = 1024;
    dmaConfig.srcAddr = (Uint32)&CSL_I2S2_REGS->I2SRXLT1;
    //dmaConfig.destAddr = (Uint32)(i2sDmaReadBufLeft); this gives random address

    Best regards,

    Ming

  • I changed dmaConfig.dmaEvt to CSL_DMA_EVT_I2S2_RX, but it does not help. DMA1 does not transfer samples to my array. 

  • Hi Pawel,

    Why do you comment out the following line?

     //dmaConfig.destAddr       = (Uint32)(i2sDmaReadBufLeft); this gives random address.

    It basically let the DMA copy the I2S data to the default address for dmaConfig.destAddr.

    Best regards,

    Ming

  • I uncommented this line but it did not help. I did this because in debug mode I saw that address in registers is different then address of my array when I write it in this way: dmaConfig.destAddr       = (Uint32)(i2sDmaReadBufLeft);

  • Hi Pawel,

    First of all the address in dmaConfig.destAddr is the starting address. The address in the DMA registers are the current DMA address. It should be increasing along with the DMA data copy.

    This issue sounds like the DMA setup issue.

    Can you share the source code, linker command file and CCS project with us, so that we can do further debugging.

    The other method is to start with the C55 CSL I2S DMA example and then compare it with your code.

    Best regards,

    Ming 

  • Hi Ming,

    this is my source code for main.c: 

    #include "codec_3206.h"
    
    #define SAMPLE_NUMBER 1024
    CSL_DMA_Handle      dmaHandleRxL;
    CSL_DMA_Handle      dmaHandleRxR;
    CSL_DMA_Handle      dmaHandleTxL;
    CSL_DMA_Handle      dmaHandleTxR;
    CSL_DMA_Config      dmaConfig;
    CSL_DMA_Config      getdmaConfig;
    CSL_DMA_ChannelObj  dmaObj;
    CSL_Status          status;
    
    Uint16 i2sDmaReadBufLeft[SAMPLE_NUMBER];
    Uint16 i2sDmaReadBufRight[SAMPLE_NUMBER];
    Uint16 Test=0;
    
    extern void VECSTART(void);
    interrupt void dma_isr(void);
    TEST_STATUS initialize_dma(void);
    
    int main(void)
    {
        // Initialize the platform
        status = initPlatform();
        if(status != Platform_EOK)
        {
            printf("Systen_init Failed\n\r");
            return (-1);
        }
        status = initialize_dma();
        if(status != 0)
        {
            printf("DMA_init Failed\n\r");
            return (-1);
        }
        // Initialize the codec
        status = initialize_codec();
        if(status != 0)
        {
            printf("Codec_init Failed\n\r");
            return (-1);
        }
    
        //Int16  data1, data2;  //for testing stereo
        while(1){
    
                    //I2S_readLeft(&data1);
                    //I2S_readRight(&data2);
                    //I2S_writeLeft(data1);
                    //I2S_writeRight(data2);
        }
    
        return (0);
    
    }
    
    TEST_STATUS initialize_dma(void){
        status = DMA_init();
        //Config left read
        dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
        dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;
        dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;
        dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;
        dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S2_RX;
        dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;
        dmaConfig.chanDir      = CSL_DMA_READ;
        dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;
        dmaConfig.dataLen      = 1024;
        dmaConfig.srcAddr      = (Uint32)&CSL_I2S2_REGS->I2SRXLT1;
        dmaConfig.destAddr       = (Uint32)(i2sDmaReadBufLeft);
    
        IRQ_globalDisable();
        IRQ_clearAll();
        IRQ_disableAll();
        IRQ_setVecs((Uint32)&VECSTART);
        IRQ_clear(DMA_EVENT);
        IRQ_plug (DMA_EVENT, &dma_isr);
        IRQ_enable(DMA_EVENT);
        IRQ_globalEnable();
    
        dmaHandleRxL = DMA_open((CSL_DMAChanNum)6,&dmaObj, &status);
        status = DMA_config(dmaHandleRxL, &dmaConfig);
    
        //Config left write
        dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
        dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;
        dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;
        dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;
        dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S2_TX;
        dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;
        dmaConfig.chanDir      = CSL_DMA_WRITE;
        dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;
        dmaConfig.dataLen      = 1024;
        dmaConfig.srcAddr      = (Uint32)i2sDmaReadBufLeft;
        dmaConfig.destAddr       = (Uint32)&CSL_I2S2_REGS->I2STXLT1;
    
        dmaHandleTxL = DMA_open((CSL_DMAChanNum)4,&dmaObj, &status);
        status = DMA_config(dmaHandleTxL, &dmaConfig);
    
        //Config right read
            dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
            dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;
            dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;
            dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;
            dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S2_RX;
            dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;
            dmaConfig.chanDir      = CSL_DMA_READ;
            dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;
            dmaConfig.dataLen      = 1024;
            dmaConfig.srcAddr      = (Uint32)&CSL_I2S2_REGS->I2SRXRT1;
            dmaConfig.destAddr       = (Uint32)i2sDmaReadBufRight;
    
            dmaHandleRxR = DMA_open((CSL_DMAChanNum)7,&dmaObj, &status);
            status = DMA_config(dmaHandleRxR, &dmaConfig);
    
            //Config right write
               dmaConfig.pingPongMode = CSL_DMA_PING_PONG_DISABLE;
               dmaConfig.autoMode     = CSL_DMA_AUTORELOAD_ENABLE;
               dmaConfig.burstLen     = CSL_DMA_TXBURST_1WORD;
               dmaConfig.trigger      = CSL_DMA_EVENT_TRIGGER;
               dmaConfig.dmaEvt       = CSL_DMA_EVT_I2S2_TX;
               dmaConfig.dmaInt       = CSL_DMA_INTERRUPT_ENABLE;
               dmaConfig.chanDir      = CSL_DMA_WRITE;
               dmaConfig.trfType      = CSL_DMA_TRANSFER_IO_MEMORY;
               dmaConfig.dataLen      = 1024;
               dmaConfig.srcAddr      = (Uint32)i2sDmaReadBufRight;
               dmaConfig.destAddr       = (Uint32)&CSL_I2S2_REGS->I2STXRT1;
    
               dmaHandleTxR = DMA_open((CSL_DMAChanNum)5,&dmaObj, &status);
               status = DMA_config(dmaHandleTxR, &dmaConfig);
    
               //status = DMA_start(dmaHandleRxL);  //this functions did not start DMA
               //status = DMA_start(dmaHandleRxR);
               //status = DMA_start(dmaHandleTxL);
               //status = DMA_start(dmaHandleTxR);
    
                //start channel with sync
               dmaHandleRxL->dmaRegs->DMACH2TCR2 |= 0x8004;
               //dmaHandleTxL->dmaRegs->DMACH0TCR2 |= 0x8004;
               dmaHandleRxR->dmaRegs->DMACH3TCR2 |= 0x8004;
               //dmaHandleTxR->dmaRegs->DMACH1TCR2 |= 0x8004;
        return (status);
    }
    
    
    interrupt void dma_isr(void)
    {
        int ifrValue;
    
        ifrValue = CSL_SYSCTRL_REGS->DMAIFR;
        CSL_SYSCTRL_REGS->DMAIFR |= ifrValue;
        Test++;
    }
    

    this is code for codec configuration:

    #include "codec_3206.h"
    
    CSL_I2sHandle   hI2s = 0;
    
    /**
     *
     * \brief This function used to Enable and initalize the I2S module
     *
     * \param void
     *
     * \return
     * \n      TEST_PASS  - Test Passed
     * \n      TEST_FAIL  - Test Failed
     *
     */
    TEST_STATUS initialise_i2s_interface(void)
    {
        I2S_Config      hwConfig;
        Int16           result = 0;
    
        /* Open the device with instance 0 */
        hI2s = I2S_open(I2S_INSTANCE2, DMA_POLLED, I2S_CHAN_STEREO); //I2S_POLLED
    
        /* Set the value for the configure structure */
        hwConfig.dataType           = I2S_STEREO_ENABLE;
        hwConfig.loopBackMode       = I2S_LOOPBACK_DISABLE;
        hwConfig.fsPol              = I2S_FSPOL_LOW;
        hwConfig.clkPol             = I2S_RISING_EDGE;
        hwConfig.datadelay          = I2S_DATADELAY_ONEBIT;
        hwConfig.datapack           = I2S_DATAPACK_ENABLE;
        hwConfig.signext            = I2S_SIGNEXT_DISABLE;
        hwConfig.wordLen            = I2S_WORDLEN_32;
        hwConfig.i2sMode            = I2S_SLAVE;
        hwConfig.FError             = I2S_FSERROR_ENABLE;
        hwConfig.OuError            = I2S_OUERROR_ENABLE;
    
        /* Configure hardware registers */
        result += I2S_setup(hI2s, &hwConfig);
        result += I2S_transEnable(hI2s, TRUE);
    
        return result;
    
    }
    
    /**
     *
     * \brief This function Reads incoming I2S left channel word and writes it
     *      to the location of "data".
     *
     * \param   *data - Pointer to location if I2S data destination
     *
     * \return void
     *
     */
    void I2S_readLeft(Int16* data)
    {
        ioport  CSL_I2sRegs   *regs;
    
        regs = hI2s->hwRegs;
        while((0x08 & regs->I2SINTFL) == 0);  // Wait for receive interrupt to be pending
        *data = regs->I2SRXLT1 ;              // 16 bit left channel receive audio data
    }
    
    /**
     *
     * \brief This function used to Writes I2S left channel word
     *
     * \param  data -I2S left data
     *
     * \return void
     *
     */
    void I2S_writeLeft(Int16 data)
    {
        ioport  CSL_I2sRegs   *regs;
    
        regs = hI2s->hwRegs;
        while((CSL_I2S_I2SINTFL_XMITSTFL_MASK & regs->I2SINTFL) == 0);  // Wait for transmit interrupt to be pending
        regs->I2STXLT1 = (data) ;            // 16 bit left channel transmit audio data
    }
    
    /**
     *
     * \brief This function Reads incoming I2S right channel word and writes it
     *      to the location of "data".
     *
     * \param   *data - Pointer to location if I2S data destination
     *
     * \return void
     *
     */
    void I2S_readRight(Int16* data)
    {
        ioport  CSL_I2sRegs   *regs;
    
        regs = hI2s->hwRegs;
    //  while((0x08 & regs->I2SINTFL) == 0);  // Wait for receive interrupt to be pending
        *data = regs->I2SRXRT1 ;              // 16 bit left channel receive audio data
    }
    
    /**
     *
     * \brief This function used to Writes I2S right channel word
     *
     * \param  data -I2S right data
     *
     * \return void
     *
     */
    void I2S_writeRight(Int16 data)
    {
        ioport  CSL_I2sRegs   *regs;
    
        regs = hI2s->hwRegs;
    //  while((CSL_I2S_I2SINTFL_XMITSTFL_MASK & regs->I2SINTFL) == 0);  // Wait for transmit interrupt to be pending
        regs->I2STXRT1 = (data) ;              // 16 bit left channel transmit audio data
    }
    
    /**
     *
     * \brief This function used to Enable and initalize the I2C module
     *         The I2C clk is set to run at 100 KHz
     *
     * \param    testArgs   [IN]   Test arguments
     *
     * \return
     * \n      TEST_PASS  - Test Passed
     * \n      TEST_FAIL  - Test Failed
     *
     */
    TEST_STATUS initialise_i2c_interface(void *testArgs)
    {
        CSL_Status         status;
        CSL_I2cConfig         i2cConfig;
    
        status = I2C_init(CSL_I2C0);
    
        /* Configure I2C module for write */
        i2cConfig.icoar  = CSL_I2C_ICOAR_DEFVAL;
        i2cConfig.icimr  = CSL_I2C_ICIMR_DEFVAL;
        i2cConfig.icclkl = 20;
        i2cConfig.icclkh = 20;
        i2cConfig.icsar  = CSL_I2C_ICSAR_DEFVAL;
        i2cConfig.icmdr  = CSL_I2C_ICMDR_WRITE_DEFVAL;
        i2cConfig.icemdr = CSL_I2C_ICEMDR_DEFVAL;
        i2cConfig.icpsc  = 20;
    
        status |= I2C_config(&i2cConfig);
    
        return 0;
    
    }
    
    /**
     *
     * \brief This function used to write into the audio codec registers
     *
     * \param testArgs  regnum - register number
     *                  regVal - register data
     *
     * \return
     * \n      TEST_PASS  - Test Passed
     * \n      TEST_FAIL  - Test Failed
     *
     */
    TEST_STATUS AIC3206_write(Uint16 regnum, Uint16 regval)
    {
        Int16 retVal;
        Uint16 startStop            = ((CSL_I2C_START) | (CSL_I2C_STOP));
        Uint16 cmd[2];
        cmd[0] = regnum & 0x007F;       // 7-bit Device Register
        cmd[1] = regval;                // 8-bit Register Data
    
        C55x_delay_msec(3);
    
        /* I2C Write */
        retVal = I2C_write(cmd, 2, AIC3206_I2C_ADDR,
                 TRUE, startStop, CSL_I2C_MAX_TIMEOUT);
         if(retVal != 0)
         {
            C55x_msgWrite("I2C Write failed\n\r");
            //return -1;
         }
    
         return (0);
    }
    
    TEST_STATUS initialize_codec(void){
        Int16 retVal;
    
        /* Enable clocks to all peripherals */
        CSL_SYSCTRL_REGS->PCGCR1 = 0x0000;
        CSL_SYSCTRL_REGS->PCGCR2 = 0x0000;
    
        retVal =  SYS_setEBSR(CSL_EBSR_FIELD_PPMODE,
                              CSL_EBSR_PPMODE_1);    // Configure Parallel Port for I2S2
        retVal |= SYS_setEBSR(CSL_EBSR_FIELD_SP1MODE,
                                 CSL_EBSR_SP1MODE_1);  // Serial Port mode 1 (I2S1 and GP[11:10]).
        retVal = initialise_i2c_interface(NULL);
        if(retVal != 0)
        {
            C55x_msgWrite("I2C initialisation failed\n\r");
            return (TEST_FAIL);
        }
    
        /* Configure AIC3206 */
        AIC3206_write( 0,  0x00 );  // Select page 0
        AIC3206_write( 1,  0x01 );  // Reset codec
        C55x_delay_msec(1);         // Wait 1ms after reset
        AIC3206_write( 0,  0x01 );  // Select page 1
        AIC3206_write( 1,  0x08 );  // Disable crude AVDD generation from DVDD
        AIC3206_write( 2,  0x01 );  // Enable Analog Blocks, use LDO power
        AIC3206_write( 123,0x05 );  // Force reference to power up in 40ms
        C55x_delay_msec(40);        // Wait at least 40ms
        AIC3206_write( 0,  0x00 );  // Select page 0
    
        /* PLL and Clocks config and Power Up  */
        AIC3206_write( 27, 0x0d );  // BCLK and WCLK are set as o/p; AIC3206(Master)
        AIC3206_write( 28, 0x00 );  // Data ofset = 0
        AIC3206_write( 4,  0x03 );  // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
        AIC3206_write( 6,  0x07 );  // PLL setting: J=7
        AIC3206_write( 7,  0x06 );  // PLL setting: HI_BYTE(D=1680)
        AIC3206_write( 8,  0x90 );  // PLL setting: LO_BYTE(D=1680)
        AIC3206_write( 30, 0x88 );  // For 32 bit clocks per frame in Master mode ONLY
                                    // BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
        AIC3206_write( 5,  0x91 );  // PLL setting: Power up PLL, P=1 and R=1
        C55x_delay_msec(1);         // Wait for PLL to come up
        AIC3206_write( 13, 0x00 );  // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
        AIC3206_write( 14, 0x80 );  // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
        AIC3206_write( 20, 0x80 );  // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
        AIC3206_write( 11, 0x82 );  // Power up NDAC and set NDAC value to 2
        AIC3206_write( 12, 0x87 );  // Power up MDAC and set MDAC value to 7
        AIC3206_write( 18, 0x87 );  // Power up NADC and set NADC value to 7
        AIC3206_write( 19, 0x82 );  // Power up MADC and set MADC value to 2
    
        /* DAC ROUTING and Power Up */
        AIC3206_write( 0,  0x01 );  // Select page 1
        AIC3206_write( 12, 0x08 );  // LDAC AFIR routed to HPL
        AIC3206_write( 13, 0x08 );  // RDAC AFIR routed to HPR
        AIC3206_write( 0,  0x00 );  // Select page 0
        AIC3206_write( 64, 0x02 );  // Left vol=right vol
        AIC3206_write( 65, 0x20 );  // Left DAC gain to 0dB VOL; Right tracks Left
        AIC3206_write( 63, 0xd4 );  // Power up left,right data paths and set channel
        AIC3206_write( 0,  0x01 );  // Select page 1
        AIC3206_write( 16, 0x00 );  // Unmute HPL , 0dB gain
        AIC3206_write( 17, 0x00 );  // Unmute HPR , 0dB gain
        AIC3206_write( 9 , 0x30 );  // Power up HPL,HPR
        C55x_delay_msec(1 );        // Wait 1 msec
    
        /* ADC ROUTING and Power Up */
        AIC3206_write( 0,  0x01 );  // Select page 1
        AIC3206_write( 52, 0x30 );  // STEREO 1 Jack
                                    // IN2_L to LADC_P through 40 kohm
        AIC3206_write( 55, 0x33 );  // IN2_R to RADC_P through 40 kohmm
        AIC3206_write( 54, 0x03 );  // CM_1 (common mode) to LADC_M through 40 kohm
        AIC3206_write( 57, 0xc0 );  // CM_1 (common mode) to RADC_M through 40 kohm
        AIC3206_write( 59, 0x00 );  // MIC_PGA_L unmute
        AIC3206_write( 60, 0x00 );  // MIC_PGA_R unmute
        AIC3206_write( 0,  0x00 );  // Select page 0
        AIC3206_write( 81, 0xc0 );  // Powerup Left and Right ADC
        AIC3206_write( 82, 0x00 );  // Unmute Left and Right ADC
        AIC3206_write( 0,  0x00 );  // Select page 0
        C55x_delay_msec(1 );        // Wait 1 msec
    
        /* Initialize I2S */
        initialise_i2s_interface();
    
        //I2S_close(hI2s);    // Disble I2S
        //AIC3206_write( 1, 0x01 );  // Reset codec
    
        return 0;
    
    }
    
    
    

    I pushed whole project to my github, here is the link to repo:

    student180529/BOOST5545ULP_DEBUG (github.com)

  • Hi Pawel,

    I saw two issues with the code you sent:

    1. The i2sDmaReadBufLeft and i2sDmaReadBufRight should be 4 byte aligned (#pragma DATA_ALIGN(i2sDmaReadBufLeft, 4);), because the DMA buffer has to be at least 4 byte aligned.

    2. The destAddr or srcAddr for DMA configuration should be &CSL_I2S2_REGS->I2STXRT0, &CSL_I2S2_REGS->I2STXLT0, &CSL_I2S2_REGS->I2SRXRT0 and &CSL_I2S2_REGS->I2SRXLT0. See I2sDmaInit() in c55xx_csl\demos\out_of_box\c5545\c5545bp_software_01.01.00.00\source_code\c5545bp_audio_demo\src\audio_data_collection.c for details.

    Best regards,

    Ming

  • Hi Ming,

    I changed my code according to Your` s suggestions, but it did not help. 

    Only when I made changes in i2s configuration, DMA has started working properly. 

        hwConfig.dataFormat     = I2S_DATAFORMAT_LJUST;
        hwConfig.dataType       = I2S_STEREO_ENABLE;
        hwConfig.loopBackMode   = I2S_LOOPBACK_DISABLE;
        hwConfig.fsPol          = I2S_FSPOL_LOW;
        hwConfig.clkPol         = I2S_RISING_EDGE;
        hwConfig.datadelay      = I2S_DATADELAY_ONEBIT;
        hwConfig.datapack       = I2S_DATAPACK_ENABLE;
        hwConfig.signext        = I2S_SIGNEXT_DISABLE;
        hwConfig.wordLen        = I2S_WORDLEN_16;
        hwConfig.i2sMode        = I2S_SLAVE;
        hwConfig.clkDiv         = I2S_CLKDIV2;
        hwConfig.fsDiv          = I2S_FSDIV32;
        hwConfig.FError         = I2S_FSERROR_DISABLE;
        hwConfig.OuError        = I2S_OUERROR_DISABLE;

    Thank You for Your` s support. This forum's thread is finally closed.