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TMS320C6747: Interval of external memory (EMIFA) access

Liu Yang
Expert 5915 points
Part Number: TMS320C6747

Hi Team,

In asynchronous access to the external memory area (CE2) via EMIFA, when the access (CE2 read) from the CPU was continuously executed, the low pulse interval of CE2 was about 250 ns which was slower than expected.

The settings are as follows.
SYSTEM_CLK1: 336 MHz
SYSTEM_CLK3: 84 MHz
EMIFA.CE2CFG＝0x80000001

Reading the Datasheet Table 6-22. EMIFA Asynchronous Memory Switching Characteristics
I understood that the interval between accesses is what was defined by No.1 Turn around time(1 CLOCK of SYSCLK3 ± 3 ns).
I compiled in debug mode, but does it change by compilation modes?
Does the EMIFA asynchronous serial access automatically insert an interval of about 250 ns?
Is DMA transfer a similar operation?

Beat Regards,
Tom Liu

  • +1
    TI__Guru 68890 points

    Tom, the turnaround time is typically the time delay between a read to a write or a write to a read, not consecutive reads.  You are probably seeing a long delay with reads because you are performing single cycle reads in your code.  If you perform burst type accesses (ie longer word elements or DMA), you should see more efficient transfers.

    Regards,

    James